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2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-08-23X86: Create a directory for files that define register indexes.Gabe Black
This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
2010-08-23X86: Consolidate extra microop flags into one parameter.Gabe Black
This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor.
2010-05-23copyright: Change HP copyright on x86 code to be more friendlyNathan Binkert
2009-12-19X86: Add a common named flag for signed media operations.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate high multiplies.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate scalar media instructions.Gabe Black
2009-08-21X86: fix some simple compile issuesNathan Binkert
static should not be used for constants that are not inside a class definition.
2009-08-17X86: Rename sel to ext for media microops.Gabe Black
2009-08-17X86: Create base classes for use with media/SIMD microops.Gabe Black
2009-08-05X86: Fix how the parity flag is computed.Gabe Black
It's only for the lowest order byte, and I had the polarity wrong.
2009-07-17X86: Set up a named constant for the "fold bit" for int register indices.Gabe Black
2009-07-17X86: Shift some register flattening work into the decoder.Gabe Black
2009-07-16X86: Take limitted advantage of the compilers type checking for microop ↵Gabe Black
operands.
2009-04-23X86: Put the StoreCheck flag with the others, and don't collide with other ↵Gabe Black
flags.
2009-02-27X86: Fix segment limit checks.Gabe Black
2009-02-25X86: Add a flag to force memory accesses to happen at CPL 0.Gabe Black
2009-02-01X86: Calculate flags based on the actual result.Gabe Black
2009-01-06X86: Autogenerate macroop generateDisassemble function.Gabe Black
2009-01-06X86: Move the function that prints memory args into the inst base class.Gabe Black
2009-01-06X86: Move the macroop class out of the isa description into C++.Gabe Black
2009-01-06X86: Change indentation on microop disassembly.Gabe Black
2008-11-09X86: Fix completeAcc get call.Gabe Black
2008-09-27gcc: Add extra parens to quell warnings.Nathan Binkert
Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases.
2007-12-01X86: Reorganize segmentation and implement segment selector movs.Gabe Black
--HG-- extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
2007-11-12X86: Various fixes to indexing segmentation related registersGabe Black
--HG-- extra : convert_revision : 3d45da3a3fb38327582cfdfb72cfc4ce1b1d31af
2007-10-31String constant const-ness changes to placate g++ 4.2.Steve Reinhardt
Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). --HG-- extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
2007-10-09X86: Get rid of stray Sparc DPRINTFGabe Black
--HG-- extra : convert_revision : d98b2d95448cab4e689d01ceedaa6ad46f9ffc09
2007-10-07X86: Significantly filled out misc regs.Gabe Black
--HG-- extra : convert_revision : 4c53be6568134d65e57f5411df986fd9a89e82c9
2007-10-02X86: Fix x87 floating point stack register indexing.Gabe Black
--HG-- extra : convert_revision : b515ec20cbfc50b38aa7da6cf4d465acf9054c08
2007-09-19X86: Move the fp microops to their own file with their own base classes in ↵Gabe Black
C++ and python. --HG-- extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
2007-09-13X86: Fix how ECF is computed in genFlags, and get rid of some duplicate code.Gabe Black
--HG-- extra : convert_revision : f86330a5a9fea782ee63aaa18ca964fb6f9cef0b
2007-09-06X86: Make signed versions of partial register values available to microops.Gabe Black
--HG-- extra : convert_revision : c820d1250f505911a341ced42d4f73796ea77f87
2007-09-04X86: Add floating point micro registers.Gabe Black
--HG-- extra : convert_revision : 442a5f8b9216638e4e6898f89eacb8695719e20f
2007-08-26X86: Remove x86 code that attempted to fix misaligned accesses.Gabe Black
--HG-- extra : convert_revision : 42f68010e6498aceb7ed25da278093e99150e4df
2007-08-07X86: Added some missing parenthesis in the condition code calculation function.Gabe Black
--HG-- extra : convert_revision : 663021070a4bcc795bb44e1839b8bcec686a42f0
2007-08-07X86: Implemented and hooked in SCAS (scan string)Gabe Black
Fixed the asz assembler symbol. Adjusted the condion checks to have appropriate options. Implemented the SCAS microcode. Attached SCAS into the decoder. --HG-- extra : convert_revision : 17bf9ddae6bc2069e43b076f8f83c4e54fb7966c
2007-08-04X86: Make 64 bit unaligned accesses work as well as the other sizes.Gabe Black
There is a fundemental flaw in how unaligned accesses are supported, but this is still an improvement. --HG-- extra : convert_revision : 1c20b524ac24cd4a812c876b067495ee6a7ae29f
2007-08-01X86: Hide the irrelevant portions of the address components for load and ↵Gabe Black
store microops. --HG-- extra : convert_revision : a5ac6fefa09882f0833537e23f1ac0477bc89bb9
2007-07-30X86: Make merge and pick work with high bytes. Fix a sizing issue in pick.Gabe Black
--HG-- extra : convert_revision : 4ddc2ca8c23bb7e90a646329ebf27a013ac5e3d6
2007-07-30X86: Make register names in disassembly reflect high bytes.Gabe Black
--HG-- extra : convert_revision : e2891581e5504de0a2c8e5932fd22425cafd4fc7
2007-07-30X86: Make disassembly use the final register index. Add bits to indicate ↵Gabe Black
whether or not register indexes should be "folded". --HG-- extra : convert_revision : 4b46e71ca91e480f6e1662b7f37b75240d6598e9
2007-07-29X86: Fix a bug with mergeGabe Black
Merge was returning the value to merge in, not the actual result of the merge. --HG-- extra : convert_revision : 230b4b5064037d099ae7859edabdf5be84603849
2007-07-26X86: Add functions to read and write to an exec context.Gabe Black
These functions take care of calling the thread contexts read and write functions with the right sized data type, and handle unaligned accesses. --HG-- extra : convert_revision : b4b59ab2b22559333035185946bae3eab316c879
2007-07-20Fixed width parameter and provided a parameter to flip the carry bit on ↵Gabe Black
subtract. --HG-- extra : convert_revision : d01bb791b000a2fdfc8600f8fb2f8aadd52b0b63
2007-07-17Make disassembled x86 register indices reflect their size.Gabe Black
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly. --HG-- extra : convert_revision : d495ac4f5756dc55a5f71953ff6963b3c030e6cb
2007-07-17Add in support for condition code flags.Gabe Black
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented. --HG-- extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f
2007-07-14Pull some hard coded base classes out of the isa description.Gabe Black
--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
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