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path: root/src/arch/x86/insts
AgeCommit message (Collapse)Author
2009-02-25X86: Add a flag to force memory accesses to happen at CPL 0.Gabe Black
2009-02-01X86: Calculate flags based on the actual result.Gabe Black
2009-01-06X86: Autogenerate macroop generateDisassemble function.Gabe Black
2009-01-06X86: Move the function that prints memory args into the inst base class.Gabe Black
2009-01-06X86: Move the macroop class out of the isa description into C++.Gabe Black
2009-01-06X86: Change indentation on microop disassembly.Gabe Black
2008-11-09X86: Fix completeAcc get call.Gabe Black
2008-09-27gcc: Add extra parens to quell warnings.Nathan Binkert
Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases.
2007-12-01X86: Reorganize segmentation and implement segment selector movs.Gabe Black
--HG-- extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
2007-11-12X86: Various fixes to indexing segmentation related registersGabe Black
--HG-- extra : convert_revision : 3d45da3a3fb38327582cfdfb72cfc4ce1b1d31af
2007-10-31String constant const-ness changes to placate g++ 4.2.Steve Reinhardt
Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). --HG-- extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
2007-10-09X86: Get rid of stray Sparc DPRINTFGabe Black
--HG-- extra : convert_revision : d98b2d95448cab4e689d01ceedaa6ad46f9ffc09
2007-10-07X86: Significantly filled out misc regs.Gabe Black
--HG-- extra : convert_revision : 4c53be6568134d65e57f5411df986fd9a89e82c9
2007-10-02X86: Fix x87 floating point stack register indexing.Gabe Black
--HG-- extra : convert_revision : b515ec20cbfc50b38aa7da6cf4d465acf9054c08
2007-09-19X86: Move the fp microops to their own file with their own base classes in ↵Gabe Black
C++ and python. --HG-- extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
2007-09-13X86: Fix how ECF is computed in genFlags, and get rid of some duplicate code.Gabe Black
--HG-- extra : convert_revision : f86330a5a9fea782ee63aaa18ca964fb6f9cef0b
2007-09-06X86: Make signed versions of partial register values available to microops.Gabe Black
--HG-- extra : convert_revision : c820d1250f505911a341ced42d4f73796ea77f87
2007-09-04X86: Add floating point micro registers.Gabe Black
--HG-- extra : convert_revision : 442a5f8b9216638e4e6898f89eacb8695719e20f
2007-08-26X86: Remove x86 code that attempted to fix misaligned accesses.Gabe Black
--HG-- extra : convert_revision : 42f68010e6498aceb7ed25da278093e99150e4df
2007-08-07X86: Added some missing parenthesis in the condition code calculation function.Gabe Black
--HG-- extra : convert_revision : 663021070a4bcc795bb44e1839b8bcec686a42f0
2007-08-07X86: Implemented and hooked in SCAS (scan string)Gabe Black
Fixed the asz assembler symbol. Adjusted the condion checks to have appropriate options. Implemented the SCAS microcode. Attached SCAS into the decoder. --HG-- extra : convert_revision : 17bf9ddae6bc2069e43b076f8f83c4e54fb7966c
2007-08-04X86: Make 64 bit unaligned accesses work as well as the other sizes.Gabe Black
There is a fundemental flaw in how unaligned accesses are supported, but this is still an improvement. --HG-- extra : convert_revision : 1c20b524ac24cd4a812c876b067495ee6a7ae29f
2007-08-01X86: Hide the irrelevant portions of the address components for load and ↵Gabe Black
store microops. --HG-- extra : convert_revision : a5ac6fefa09882f0833537e23f1ac0477bc89bb9
2007-07-30X86: Make merge and pick work with high bytes. Fix a sizing issue in pick.Gabe Black
--HG-- extra : convert_revision : 4ddc2ca8c23bb7e90a646329ebf27a013ac5e3d6
2007-07-30X86: Make register names in disassembly reflect high bytes.Gabe Black
--HG-- extra : convert_revision : e2891581e5504de0a2c8e5932fd22425cafd4fc7
2007-07-30X86: Make disassembly use the final register index. Add bits to indicate ↵Gabe Black
whether or not register indexes should be "folded". --HG-- extra : convert_revision : 4b46e71ca91e480f6e1662b7f37b75240d6598e9
2007-07-29X86: Fix a bug with mergeGabe Black
Merge was returning the value to merge in, not the actual result of the merge. --HG-- extra : convert_revision : 230b4b5064037d099ae7859edabdf5be84603849
2007-07-26X86: Add functions to read and write to an exec context.Gabe Black
These functions take care of calling the thread contexts read and write functions with the right sized data type, and handle unaligned accesses. --HG-- extra : convert_revision : b4b59ab2b22559333035185946bae3eab316c879
2007-07-20Fixed width parameter and provided a parameter to flip the carry bit on ↵Gabe Black
subtract. --HG-- extra : convert_revision : d01bb791b000a2fdfc8600f8fb2f8aadd52b0b63
2007-07-17Make disassembled x86 register indices reflect their size.Gabe Black
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly. --HG-- extra : convert_revision : d495ac4f5756dc55a5f71953ff6963b3c030e6cb
2007-07-17Add in support for condition code flags.Gabe Black
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented. --HG-- extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f
2007-07-14Pull some hard coded base classes out of the isa description.Gabe Black
--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
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