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path: root/src/arch/x86/isa.cc
AgeCommit message (Expand)Author
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-12-06x86: Split apart x87's FSW and TOP, and add a missing break.Gabe Black
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-02-06x86: create function to check miscreg validitySteve Reinhardt
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-07-04x86: Adjust the size of the values written to the x87 misc registersNikos Nikoleris
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
2013-01-07arch: Add support for invalidating TLBs when drainingAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-04X86: Move address based decode caching in front of the predecoder.Gabe Black
2012-12-30x86: implement x87 fp instruction fnstswNilay Vaish
2010-08-17x86: minor checkpointing bug fixesSteve Reinhardt
2009-11-04build: fix compile problems pointed out by gcc 4.4Nathan Binkert
2009-07-17X86: Shift some register flattening work into the decoder.Gabe Black
2009-07-09X86: Fold the MiscRegFile all the way into the ISA object.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black