gem5 - gem5

Age	Commit message (Collapse)	Author
2014-01-24	arch: Make all register index flattening const	Andreas Hansson
	This patch makes all the register index flattening methods const for all the ISAs. As part of this, readMiscRegNoEffect for ARM is also made const.
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
	With ARMv8 support the same misc register id results in accessing different registers depending on the current mode of the processor. This patch adds the same orthogonality to the misc register file as the others (int, float, cc). For all the othre ISAs this is currently a null-implementation. Additionally, a system variable is added to all the ISA objects.
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
	Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-02-19	scons: Add warning for overloaded virtual functions	Andreas Hansson
	Fix the ISA startup warnings
2013-01-12	x86: Changes to decoder, corrects 9376	Nilay Vaish
	The changes made by the changeset 9376 were not quite correct. The patch made changes to the code which resulted in decoder not getting initialized correctly when the state was restored from a checkpoint. This patch adds a startup function to each ISA object. For x86, this function sets the required state in the decoder. For other ISAs, the function is empty right now.
2013-01-07	arch: Move the ISA object to a separate section	Andreas Sandberg
	After making the ISA an independent SimObject, it is serialized automatically by the Python world. Previously, this just resulted in an empty ISA section. This patch moves the contents of the ISA to that section and removes the explicit ISA serialization from the thread contexts, which makes it behave like a normal SimObject during serialization. Note: This patch breaks checkpoint backwards compatibility! Use the cpt_upgrader.py utility to upgrade old checkpoints to the new format.
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
	The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2013-01-04	X86: Move address based decode caching in front of the predecoder.	Gabe Black
	The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2011-04-15	includes: sort all includes	Nathan Binkert

2010-08-23	X86: Create a directory for files that define register indexes.	Gabe Black
	This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
2009-07-17	X86: Set up a named constant for the "fold bit" for int register indices.	Gabe Black

2009-07-17	X86: Shift some register flattening work into the decoder.	Gabe Black

2009-07-09	X86: Fold the MiscRegFile all the way into the ISA object.	Gabe Black

2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black

2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
	This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.