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2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
This patch encompasses several interrelated and interdependent changes to the ISA generation step. The end goal is to reduce the size of the generated compilation units for instruction execution and decoding so that batch compilation can proceed with all CPUs active without exhausting physical memory. The ISA parser (src/arch/isa_parser.py) has been improved so that it can accept 'split [output_type];' directives at the top level of the grammar and 'split(output_type)' python calls within 'exec {{ ... }}' blocks. This has the effect of "splitting" the files into smaller compilation units. I use air-quotes around "splitting" because the files themselves are not split, but preprocessing directives are inserted to have the same effect. Architecturally, the ISA parser has had some changes in how it works. In general, it emits code sooner. It doesn't generate per-CPU files, and instead defers to the C preprocessor to create the duplicate copies for each CPU type. Likewise there are more files emitted and the C preprocessor does more substitution that used to be done by the ISA parser. Finally, the build system (SCons) needs to be able to cope with a dynamic list of source files coming out of the ISA parser. The changes to the SCons{cript,truct} files support this. In broad strokes, the targets requested on the command line are hidden from SCons until all the build dependencies are determined, otherwise it would try, realize it can't reach the goal, and terminate in failure. Since build steps (i.e. running the ISA parser) must be taken to determine the file list, several new build stages have been inserted at the very start of the build. First, the build dependencies from the ISA parser will be emitted to arch/$ISA/generated/inc.d, which is then read by a new SCons builder to finalize the dependencies. (Once inc.d exists, the ISA parser will not need to be run to complete this step.) Once the dependencies are known, the 'Environments' are made by the makeEnv() function. This function used to be called before the build began but now happens during the build. It is easy to see that this step is quite slow; this is a known issue and it's important to realize that it was already slow, but there was no obvious cause to attribute it to since nothing was displayed to the terminal. Since new steps that used to be performed serially are now in a potentially-parallel build phase, the pathname handling in the SCons scripts has been tightened up to deal with chdir() race conditions. In general, pathnames are computed earlier and more likely to be stored, passed around, and processed as absolute paths rather than relative paths. In the end, some of these issues had to be fixed by inserting serializing dependencies in the build. Minor note: For the null ISA, we just provide a dummy inc.d so SCons is never compelled to try to generate it. While it seems slightly wrong to have anything in src/arch/*/generated (i.e. a non-generated 'generated' file), it's by far the simplest solution.
2014-05-09arch: remove inline specifiers on all inst constrs, all ISAsCurtis Dunham
With (upcoming) separate compilation, they are useless. Only link-time optimization could re-inline them, but ideally feedback-directed optimization would choose to do so only for profitable (i.e. common) instructions.
2012-06-04X86: Ensure that the CPUID instruction always writes its outputs.Gabe Black
The CPUID instruction was implemented so that it would only write its results if the instruction was successful. This works fine on the simple CPU where unwritten registers retain their old values, but on a CPU like O3 with renaming this is broken. The instruction needs to write the old values back into the registers explicitly if they aren't being changed.
2011-06-02copyright: clean up copyright blocksNathan Binkert
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-22X86: Make nop a regular, non-microcoded instruction.Gabe Black
Code in the CPUs that need a nop to carry a fault can't easily deal with a microcoded nop. This instruction format provides for one that isn't. --HG-- rename : src/arch/x86/isa/formats/syscall.isa => src/arch/x86/isa/formats/nop.isa
2010-09-14X86: Make unrecognized instructions behave better in x86.Gabe Black
2010-08-23X86: Get rid of the flagless microop constructor.Gabe Black
This will reduce clutter in the source and hopefully speed up compilation.
2010-08-23X86: Mark serializing macroops and regular instructions as such.Gabe Black
2010-05-23copyright: Change HP copyright on x86 code to be more friendlyNathan Binkert
2009-01-06X86: Hook in the M5 pseudo insts.Gabe Black
2008-10-12X86: Implement CPUID with a magical function instead of microcode.Gabe Black
2007-10-18X86: Make the "fault" microop predicated.Gabe Black
--HG-- extra : convert_revision : 48dae1f3c680636833c137fe6b95b37ae84e188c
2007-10-09X86: Get rid of BasicOperate format which wasn't used and referred to ↵Gabe Black
SparcStaticInst --HG-- extra : convert_revision : 5d2eac9a4b3f0fe5e3c3554d91acf8fee368c9dc
2007-10-02X86: Distinguish between the rep and repe prefixes.Gabe Black
STOS and MOVS only accept the rep prefix which always loops until rcx becomes 0. The other string instructions accept repe (same encoding as rep) and repne which also check the condition code flags each iteration. --HG-- extra : convert_revision : 544149f640302070810fb53e53bfeb0e87160ffc
2007-08-07X86: Add a format to handle string instructions which can use the repe and ↵Gabe Black
repne prefixes. --HG-- extra : convert_revision : 205fbbb947258bc0ef2915e22d5b32a3df1a1ce2
2007-07-30X86: missed a file which adds a "fold" bit.Gabe Black
--HG-- extra : convert_revision : 2c8eea425221d069a9bb888c8f18839843061899
2007-07-19x86 fixesGabe Black
Make the emulation environment consider the rex prefix. Implement and hook in forms of j, jmp, cmp, syscall, movzx Added a format for an instruction to carry a call to the SE mode syscalls system Made memory instructions which refer to the rip do so directly Made the operand size overridable in the microassembly Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on Added an explicit "rax" operand for the syscall format Implemented syscall returns. --HG-- extra : convert_revision : ae84bd8c6a1d400906e17e8b8c4185f2ebd4c5f2
2007-07-18Fix the panic in the "error" format for x86,Gabe Black
--HG-- extra : convert_revision : bd0715b5b63665f9160082d67c5b5d90d2405c5c
2007-07-14Pull some hard coded base classes out of the isa description.Gabe Black
--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
2007-06-20Implement rip relative addressing and put in some missing loads and stores.Gabe Black
--HG-- extra : convert_revision : 99053414cef40f13c5226871a72909b2622d8c26
2007-06-14Implement a handful more instructions and differentiate macroops based on ↵Gabe Black
the operand types they expect. --HG-- extra : convert_revision : f9c8e694a8c0eb33b988657dca03ab495b65bee8
2007-06-12Use objects to pass around output code, and fix/implement a few things.Gabe Black
src/arch/x86/isa/formats/multi.isa: Make the formats use objects to pass around output code. --HG-- extra : convert_revision : 428915bda22e848befac15097f56375c1818426e
2007-06-08Fix up a potentially misleading comment.Gabe Black
--HG-- extra : convert_revision : 58d37d8cc8e41c9640038d6dddae4cb5649638aa
2007-06-08Big changes to use the new microcode assembler.Gabe Black
--HG-- extra : convert_revision : 7d1a43c5791a2e7e30533746da3dd7036a5b8799
2007-04-10Reworked x86 a bitGabe Black
--HG-- extra : convert_revision : def1a30e54b59c718c451a631a1be6f8e787e843
2007-04-06Refactored the x86 isa description some more. There should be more ↵Gabe Black
seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere. --HG-- rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa extra : convert_revision : 5ab40eedf574fce438d9fe90e00a496dc95c8bcf
2007-04-06Clean up the macroop code.Gabe Black
--HG-- extra : convert_revision : 3cf83c3e038fece6190dbb91f56deb0498c9a70d
2007-04-04Reworking how x86's isa description works. I'm adopting the following ↵Gabe Black
definitions to make figuring out what's what a little easier: MicroOp: A single operation actually implemented in hardware. MacroOp: A collection of microops which are executed as a unit. Instruction: An architected instruction which can be implemented with a macroop or a microop. --HG-- extra : convert_revision : 1cfc8409cc686c75220767839f55a30551aa6f13
2007-04-03A batch of changes and fixes. Macroops are now generated automatically, ↵Gabe Black
multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented. --HG-- extra : convert_revision : 518059f47e11df50aa450d4a322ef2ac069c99c9
2007-03-29Made the MultiOp format do a little more. It now sets up single microop ↵Gabe Black
instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support. --HG-- extra : convert_revision : 1a0a4b36afce8255e23e3cdd7a85c1392dda5f72
2007-03-21Start implementing groups of instructions which do the same thing on ↵Gabe Black
different sets of inputs. --HG-- extra : convert_revision : 6a5be61831588f801965dd4e80cb52f28911c320
2007-03-21Break out the one and two byte opcodes into different files. Also change ↵Gabe Black
what bits decode is done on to reflect where clumps of instructions are. --HG-- extra : convert_revision : 8768676eac25e6a4f0dc50ce2dc576bdcdd6e025
2007-03-15Make the predecoder an object with it's own switched header file. Start ↵Gabe Black
adding predecoding functionality to x86. src/arch/SConscript: src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/cpu/base.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/static_inst.hh: src/arch/alpha/predecoder.hh: src/arch/mips/predecoder.hh: src/arch/sparc/predecoder.hh: Make the predecoder an object with it's own switched header file. --HG-- extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
2007-03-05Stub decoder. This is probably even farther from finished than it looks...Gabe Black
--HG-- extra : convert_revision : a39a158fec4560f6eb7a6987592c473677c0b1ba