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2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2016-02-06arch, x86: add support for arrays as memory operandsSteve Reinhardt
Although the cache models support wider accesses, the ISA descriptions assume that (for the most part) memory operands are integer types, which makes it difficult to define instructions that do memory accesses larger than 64 bits. This patch adds some generic support for memory operands that are arrays of uint64_t, and specifically a 'u2qw' operand type for x86 that is an array of 2 uint64_ts (128 bits). This support is unused at this point, but will be needed shortly for cmpxchg16b. Ideally the 128-bit SSE memory accesses will also be rewritten to use this support. Support for 128-bit accesses could also have been added using the gcc __int128_t extension, which would have been less disruptive. However, although clang also supports __int128_t, it's still non-standard. Also, more importantly, this approach creates a path to defining 256- and 512-byte operands as well, which will be useful for eventual AVX support.
2013-06-18x86: Fix loading of floating point constantsAndreas Sandberg
This changeset actually fixes two issues: * The lfpimm instruction didn't work correctly when applied to a floating point constant (it did work for integers containing the bit string representation of a constant) since it used reinterpret_cast to convert a double to a uint64_t. This caused a compilation error, at least, in gcc 4.6.3. * The instructions loading floating point constants in the x87 processor didn't work correctly since they just stored a truncated integer instead of a double in the floating point register. This changeset fixes the old microcode by using lfpimm instruction instead of the limm instructions.
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2012-02-26X86: Use the M5PanicFault fault in execute methods instead of calling panic.Gabe Black
If an instruction is executed speculatively and hits a situation where it wants to panic, it should return a fault instead. If the instruction was misspeculated, the fault can be thrown away. If the instruction wasn't misspeculated, the fault will be invoked and the panic will still happen.
2011-09-30SE/FS: Use the new FullSystem constant where possible.Gabe Black
2011-09-19PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.Gabe Black
2011-07-02ISA: Use readBytes/writeBytes for all instruction level memory operations.Gabe Black
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15includes: sort all includesNathan Binkert
2011-02-13X86: Put the result used for flags in an intermediate variable.Gabe Black
Using the destination register directly causes the ISA parser to treat it as a source even if none of the original bits are used.
2011-02-13X86: Define fault objects to carry debug messages.Gabe Black
These faults can panic/warn/warn_once, etc., instead of instructions doing that themselves directly. That way, instructions can be speculatively executed, and only if they're actually going to commit will their fault be invoked and the panic, etc., happen.
2010-08-23X86: Create a directory for files that define register indexes.Gabe Black
This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
2010-05-23copyright: Change HP copyright on x86 code to be more friendlyNathan Binkert
2009-08-17X86: Implement an integer media addition microop with optional saturation.Gabe Black
2009-08-17X86: Set up a media microop framework and create mov2int and mov2fp microops.Gabe Black
2009-07-16X86: Take limitted advantage of the compilers type checking for microop ↵Gabe Black
operands.
2009-07-09X86: Fold the MiscRegFile all the way into the ISA object.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-02-25X86: Implement a basic prefetch instruction.Gabe Black
2009-02-25X86: Add a flag to force memory accesses to happen at CPL 0.Gabe Black
2009-01-06X86: Hook in the M5 pseudo insts.Gabe Black
2009-01-06X86: Move the macroop class out of the isa description into C++.Gabe Black
2008-10-12X86: Make X86's microcode ROM actually do something.Gabe Black
2008-10-12X86: Implement CPUID with a magical function instead of microcode.Gabe Black
2008-06-12X86: Add microops which panic, fatal, warn, and warn_once.Gabe Black
2007-10-02X86: Implement the ldst microop and put it in existing microcode where ↵Gabe Black
appropriate. --HG-- extra : convert_revision : f08bd725d07a501bb7a0ce91590b5d37db99c6f3
2007-09-19X86: Move the fp microops to their own file with their own base classes in ↵Gabe Black
C++ and python. --HG-- extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
2007-09-06X86: Add SSE comparison instructions and microops and move some FP microops ↵Gabe Black
to be with the other ones. --HG-- extra : convert_revision : ee0b5acde08d12c51a5282efb58d1ac72e0779af
2007-08-29X86: Add operands to handle floating point registers.Gabe Black
--HG-- extra : convert_revision : 2e8289dbd3f5dda1221014d4ed0e9450f60de0cf
2007-07-17Actually include miscregs.hhGabe Black
--HG-- extra : convert_revision : 6ebf906d2211b94f28c173f0d2da91bd446fcb2c
2007-07-14Pull some hard coded base classes out of the isa description.Gabe Black
--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
2007-06-21Get rid of an unnecessary include file.Gabe Black
--HG-- extra : convert_revision : d8d139180917f54006a5a79df4a0f206ddd39fed
2007-06-21Needed for last change set to work :PGabe Black
--HG-- extra : convert_revision : 9e57e582dd1ef2805d5adffcc0ccfd99596d9f54
2007-06-20Make memory instructions work better, add more macroop implementations, add ↵Gabe Black
an lea microop, move EmulEnv into it's own .cc and .hh. --HG-- extra : convert_revision : 1212b8463eab1c1dcba7182c487d1e9184cf9bea
2007-06-12Get rid of unnecessary namespace prototype.Gabe Black
--HG-- extra : convert_revision : 388c0d6f2af96c4d33c1fe5d42a21866a4d71556
2007-06-08Big changes to use the new microcode assembler.Gabe Black
--HG-- extra : convert_revision : 7d1a43c5791a2e7e30533746da3dd7036a5b8799
2007-04-03A batch of changes and fixes. Macroops are now generated automatically, ↵Gabe Black
multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented. --HG-- extra : convert_revision : 518059f47e11df50aa450d4a322ef2ac069c99c9
2007-03-05Stub decoder. This is probably even farther from finished than it looks...Gabe Black
--HG-- extra : convert_revision : a39a158fec4560f6eb7a6987592c473677c0b1ba
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