gem5 - gem5

Age	Commit message (Collapse)	Author
2018-01-23	arch-x86: Adding clflush, clflushopt, clwb instructions	Swapnil Haria
	This patch adds support for cache flushing instructions in x86. It piggybacks on support for similar instructions in arm ISA added by Nikos Nikoleris. I have tested each instruction using microbenchmarks. Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d Reviewed-on: https://gem5-review.googlesource.com/7401 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2010-05-23	copyright: Change HP copyright on x86 code to be more friendly	Nathan Binkert

2009-02-25	X86: Implement a basic prefetch instruction.	Gabe Black

2008-09-10	style: Remove non-leading tabs everywhere they shouldn't be. Developers ↵	Ali Saidi
	should configure their editors to not insert tabs
2007-09-19	X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.	Gabe Black
	--HG-- rename : src/arch/x86/isa/insts/sse/__init__.py => src/arch/x86/isa/insts/simd128/__init__.py extra : convert_revision : efb4405aebaa4a04f33572e7d078ceca45872d9c