gem5 - gem5

Age	Commit message (Collapse)	Author
2013-05-21	x86: mark instructions for being function call/return	Nilay Vaish
	Currently call and return instructions are marked as IsCall and IsReturn. Thus, the branch predictor does not use RAS for these instructions. Similarly, the number of function calls that took place is recorded as 0. This patch marks these instructions as they should be.
2013-04-23	x86: increment the stack pointer in lret inst	Christian Menard
	The 'lret' instruction reloads instruction pointer and code segment from the stack and then pops them. But the popping part is missing from the current implementation. This caused incorrect behavior in some code related to the Fiasco OS. Microops are being added to rectify the behavior of the instruction. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2010-05-23	copyright: Change HP copyright on x86 code to be more friendly	Nathan Binkert

2008-10-12	X86: Create a SeqOp class of microops and make Br one of them.	Gabe Black

2008-10-09	X86: Make far ret modify CS instead of some random selector.	Gabe Black

2008-06-12	X86: Change how segment loading is performed.	Gabe Black

2007-12-01	X86: First crack at far returns. This is grossly approximate.	Gabe Black
	--HG-- extra : convert_revision : 23da0338af1f7663ae5ddf2289fb45dd32f37c42
2007-10-02	X86: Put ldst into the microcode (the earlier changeset didn't really).	Gabe Black
	Also clean things up as much as possible so that faulting won't break an instruction. More microops which verify addresses are needed. --HG-- extra : convert_revision : 7c6050cb4798d287fe7d3cc4bb8c20dfa40ad2be
2007-09-19	X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.	Gabe Black
	--HG-- rename : src/arch/x86/isa/insts/sse/__init__.py => src/arch/x86/isa/insts/simd128/__init__.py extra : convert_revision : efb4405aebaa4a04f33572e7d078ceca45872d9c