| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-02-27 | X86: Make instructions that use intseg preserve all 8 bytes of their addresses. | Gabe Black | |
| 2009-02-25 | X86: Do a merge for the zero extension microop. | Gabe Black | |
| 2008-10-12 | X86: Create a SeqOp class of microops and make Br one of them. | Gabe Black | |
| 2008-06-12 | X86: Make string instructions work when rcx=0. | Gabe Black | |
| 2008-06-12 | X86: Bypass unaligned access support for register addressed MSRs. | Gabe Black | |
| 2008-01-12 | X86: Fix the general IO instructions dataSize. | Gabe Black | |
| --HG-- extra : convert_revision : 9774a52cb6a8e7632d1b1dc0706e5791cc18d238 | |||
| 2007-11-12 | X86: Change the meaning of the sext and zext width operand, and make sext ↵ | Gabe Black | |
| set zext if the sign bit is 0. --HG-- extra : convert_revision : 08bd7b4ff183038c016612d04ac73b20a255d141 | |||
| 2007-10-18 | X86: Implement the string IO instructions, ins and outs. | Gabe Black | |
| --HG-- extra : convert_revision : b021e70390d289b22a8e693cd8a99d6e7bd7d2b4 | |||
| 2007-10-18 | X86: Implement the in/out instructions. These will still need support from ↵ | Gabe Black | |
| the TLB and memory system. --HG-- extra : convert_revision : a9503248ea9efca7e5247e4f2830967f428b8215 | |||
| 2007-09-19 | X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode. | Gabe Black | |
| --HG-- rename : src/arch/x86/isa/insts/sse/__init__.py => src/arch/x86/isa/insts/simd128/__init__.py extra : convert_revision : efb4405aebaa4a04f33572e7d078ceca45872d9c | |||
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |