| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2013-05-21 | x86: mark instructions for being function call/return | Nilay Vaish | |
| Currently call and return instructions are marked as IsCall and IsReturn. Thus, the branch predictor does not use RAS for these instructions. Similarly, the number of function calls that took place is recorded as 0. This patch marks these instructions as they should be. | |||
| 2013-04-23 | x86: increment the stack pointer in lret inst | Christian Menard | |
| The 'lret' instruction reloads instruction pointer and code segment from the stack and then pops them. But the popping part is missing from the current implementation. This caused incorrect behavior in some code related to the Fiasco OS. Microops are being added to rectify the behavior of the instruction. Committed by: Nilay Vaish <nilay@cs.wisc.edu> | |||
| 2012-04-29 | X86: Fix the IMUL_R_P_I macroop. | Gabe Black | |
| The disp displacement was left off the load microop so the wrong value was used. | |||
| 2012-01-09 | X86: Add memory fence to I/O instructions | Nilay Vaish | |
| 2011-11-03 | x86: Add microop for fence | Nilay Vaish | |
| This patch adds a new microop for memory barrier. The microop itself does nothing, but since it is marked as a memory barrier, the O3 CPU should flush all the pending loads and stores before the fence to the memory system. | |||
| 2011-03-01 | X86: Mark IO reads and writes as non-speculative. | Gabe Black | |
| 2011-02-07 | X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop. | Tim Harris | |
| During SYSCALL_64, use dataSize=8 when handling new rip (ref http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit address) | |||
| 2011-02-07 | X86: Fix JMP_FAR_I to unpack a far pointer correctly. | Tim Harris | |
| JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like it should, and also putting the components in the wrong registers for use by other microcode. | |||
| 2011-02-07 | X86: Read the LDT/GDT at CPL0 when executing an iret. | Tim Harris | |
| During iret access LDT/GDT at CPL0 rather than after transition to user mode (if I'm reading the Intel IA-64 architecture spec correctly, the contents of the descriptor table are read before the CPL is updated). | |||
| 2011-02-02 | X86: Replace the stupd microop with a store/update sequence. | Gabe Black | |
| 2010-09-29 | X86: Fix the RIP relative versions of the BT, BTC, BTR, and BTS instructions. | Gabe Black | |
| 2010-08-23 | X86: Mark serializing macroops and regular instructions as such. | Gabe Black | |
| 2010-07-21 | Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses | Tushar Krishna | |
| 2010-05-23 | copyright: Change HP copyright on x86 code to be more friendly | Nathan Binkert | |
| 2009-11-10 | X86: Fix bugs in movd implementation. | Vince Weaver | |
| Unfortunately my implementation of the movd instruction had two bugs. In one case, when moving a 32-bit value into an xmm register, the lower half of the xmm register was not zero extended. The other case is that xmm was used instead of xmmlm as the source for a register move. My test case didn't notice this at first as it moved xmm0 to eax, which both have the same register number. | |||
| 2009-10-30 | X86: Implement movd_Vo_Edp on X86 | Vince Weaver | |
| This patch implements the movd_Vo_Edp series of instructions. It addresses various concerns by Gabe Black about which file the instruction belonged in, as well as supporting REX prefixed instructions properly. This instruction is needed for some of the spec2k benchmarks, most notably bzip2. | |||
| 2009-09-16 | X86: Fix checking the NT bit during an IRET. | Gabe Black | |
| 2009-08-17 | X86: Implement MOVNTI. | Gabe Black | |
| 2009-08-17 | X86: Turn the DIV and IDIV microcode into templates and generate all the ↵ | Gabe Black | |
| variants. | |||
| 2009-08-17 | X86: Remove some FIXMEs from IDIV that have been fixed. | Gabe Black | |
| 2009-08-17 | X86: Turn the CMPXCHG8B microcode into a template and generate each variant. | Gabe Black | |
| 2009-08-17 | X86: Fix a bug introduced to IDIV in a recent attempt to fix another bug. | Gabe Black | |
| 2009-08-09 | X86: Implement the CMPXCHG8B/CMPXCHG16B instruction. | Gabe Black | |
| 2009-08-09 | X86: Don't clobber the original dividend when doing signed divide. | Gabe Black | |
| 2009-08-08 | X86: Make not taken conditional moves leave the destination alone. Adjust ↵ | Gabe Black | |
| CMOVcc. The manuals from both AMD and Intel say that when writing to a 32 bit destination in 64 bit mode, the upper 32 bits of the register are filled with zeros. They also both say that the CMOV instructions leave their destination alone when their condition fails. Unfortunately, it seems that CMOV will zero extend its destination register whether or not it was supposed to actually do a move on both platforms. This seems to be the only case where this happens, but it would be hard to say for sure. | |||
| 2009-08-07 | X86: (Re)Implemented SHRD. | Gabe Black | |
| 2009-08-07 | X86: Implement SHLD. | Gabe Black | |
| 2009-08-07 | X86: Make the qaud width bswap instruction handle the fact that 32 bit ↵ | Gabe Black | |
| operations zero extend. | |||
| 2009-08-07 | X86: Don't truncate the immediate parameter for the ENTER instruction. | Gabe Black | |
| 2009-08-06 | X86: Adjust the various sizes used for the enter and leave instructions. | Gabe Black | |
| 2009-08-06 | X86: Make scas compare its operands in the right order. | Gabe Black | |
| 2009-08-06 | X86: Fix a copy/paste error for cmovnp. | Gabe Black | |
| 2009-08-05 | X86: Fix condition code setting for signed multiplies with negative results. | Gabe Black | |
| 2009-08-05 | X86: Use the new forced folding mechanism for the SAHF and LAHF instructions. | Gabe Black | |
| 2009-08-05 | X86: Fix the indexing for ah in byte division instructions. | Gabe Black | |
| 2009-08-05 | X86: Fix the indexing for ah in byte multiply instructions. | Gabe Black | |
| 2009-08-05 | X86: Set the flags on rotate left with carry instructions. | Gabe Black | |
| 2009-08-05 | X86: Set the flags for rotate right with carry instructions. | Gabe Black | |
| 2009-08-05 | X86: Set the flags on a rotate right instruction. | Gabe Black | |
| 2009-08-05 | X86: Actually set the flags on a rotate left instruction. | Gabe Black | |
| 2009-07-16 | X86: Fix a number of places where the wrong form of a microop was used. | Gabe Black | |
| 2009-07-08 | X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended. | Gabe Black | |
| 2009-05-28 | X86: Keep track of more descriptor state to accomodate KVM. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of XADD. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTR. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of CMPXCHG. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTS. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of DEC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of INC. | Gabe Black | |
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