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2019-09-19arch-x86: Change warn to warn_once for NT instructionsHoa Nguyen
Change-Id: I50353716f2a913b9b106b140644d95991879f662 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05arch-x86: implement movntq/movntdq instructionsPouya Fotouhi
Non-temporal quadword/double-quadword move instructions. This change ignores the non-temporal hint and instructions are implemented to send cacheable request to memory. This would have some "performance" impact (i.e. having some cache pollution) to get better "correctness" in behavior. Change-Id: I2052ac0970f61a54bafb7332762debcb7103202d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20288 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2010-05-23copyright: Change HP copyright on x86 code to be more friendlyNathan Binkert
2009-08-17X86: Implement the mask move instructions.Gabe Black
2009-08-17X86: Implement the instructions that move sign bits.Gabe Black
2009-08-17X86: Move the MMX version of MOVD into the simd64 directory.Gabe Black
2007-09-19X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.Gabe Black
--HG-- rename : src/arch/x86/isa/insts/sse/__init__.py => src/arch/x86/isa/insts/simd128/__init__.py extra : convert_revision : efb4405aebaa4a04f33572e7d078ceca45872d9c