gem5 - gem5

Age	Commit message (Collapse)	Author
2017-12-06	x86: Split apart x87's FSW and TOP, and add a missing break.	Gabe Black
	The FSW and TOP values are technically part of the same register, but they have very different behaviors. One of them can be renamed and float along without affecting global state, while the other requires serialization. They just need to look like the same register when read by the user. Also, there was a missing break in setMiscRegNoEffect. Change-Id: If58de0f566f65068208240f4001209fb9e1826d6 Reviewed-on: https://gem5-review.googlesource.com/6441 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2015-07-04	x86: Adjust the size of the values written to the x87 misc registers	Nikos Nikoleris
	All x87 misc registers are implemented in an array of 64 bit values but in real hardware the size of some of these registers is smaller. Previsouly all 64 bits where incorrectly set and then later read. To ensure correctness we mask the value in setMiscRegNoEffect to write only the valid bits. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-09-30	x86: Add support for FLDENV & FNSTENV	Andreas Sandberg

2010-05-23	copyright: Change HP copyright on x86 code to be more friendly	Nathan Binkert

2007-09-19	X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.	Gabe Black
	--HG-- rename : src/arch/x86/isa/insts/sse/__init__.py => src/arch/x86/isa/insts/simd128/__init__.py extra : convert_revision : efb4405aebaa4a04f33572e7d078ceca45872d9c