| Age | Commit message (Expand) | Author |
|---|
| 2018-03-14 | x86: Implement the RDTSCP instruction. | Gabe Black |
| 2018-03-14 | x86: Mark the RDTSC instruction as .serialize_before. | Gabe Black |
| 2018-03-14 | x86: Replace the .serializing directive with .serialize_(before|after). | Gabe Black |
| 2018-01-23 | arch-x86: Adding clflush, clflushopt, clwb instructions | Swapnil Haria |
| 2017-12-14 | x86: Use operand size 4 when it would be 2 for cmpxchg8b. | Gabe Black |
| 2017-12-06 | x86: Split apart x87's FSW and TOP, and add a missing break. | Gabe Black |
| 2017-12-05 | x86: LOOP's operand size defaults to 64 bits in 64 bit mode. | Gabe Black |
| 2017-02-10 | x86: Fix implicit stack addressing in 64-bit mode | Jason Lowe-Power |
| 2016-02-06 | x86: revamp cmpxchg8b/cmpxchg16b implementation | Alexandru Dutu |
| 2016-02-06 | style: remove trailing whitespace | Steve Reinhardt |
| 2015-10-06 | x86: implement rcpps and rcpss SSE insts | Steve Reinhardt |
| 2015-10-06 | x86: implement fild, fucomi, and fucomip x87 insts | Steve Reinhardt |
| 2015-07-20 | x86: x86 instruction-implementation bug fixes | David Hashe |
| 2015-07-04 | x86: Adjust the size of the values written to the x87 misc registers | Nikos Nikoleris |
| 2015-04-13 | x86: implements x87 mult/div instructions | Nilay Vaish |
| 2015-01-10 | x86 : fxsave and fxrestore missing template code | Emilio Castillo |
| 2015-01-03 | x86: implements the simd128 ADDSUBPD instruction | Maxime Martinasso |
| 2014-11-17 | x86: Fix setting segment bases in real mode. | Gabe Black |
| 2014-11-17 | x86: Fix some bugs in the real mode far jmp instruction. | Gabe Black |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2014-01-27 | x86: use lfpimm instead of limm for fptan | Nilay Vaish |
| 2014-01-27 | x86: implements x87 add/sub instructions | Nilay Vaish |
| 2014-01-27 | x86: implements fxch instruction. | Nilay Vaish |
| 2013-11-26 | x86: Implementation of Int3 and Int_Ib in long mode | Christian Menard |
| 2013-09-30 | x86: Add support for FXSAVE, FXSAVE64, FXRSTOR, and FXRSTOR64 | Andreas Sandberg |
| 2013-09-30 | x86: Add support for FLDENV & FNSTENV | Andreas Sandberg |
| 2013-09-30 | x86: Add support for loading 32-bit and 80-bit floats in the x87 | Andreas Sandberg |
| 2013-09-30 | x86: Fix re-entrancy problems in x87 store instructions | Andreas Sandberg |
| 2013-06-18 | x86: Fix loading of floating point constants | Andreas Sandberg |
| 2013-06-18 | x86: Make fprem like the fprem on a real x87 | Andreas Sandberg |
| 2013-06-18 | x86: Fix the flag handling code in FABS and FCHS | Andreas Sandberg |
| 2013-05-21 | x86: mark instructions for being function call/return | Nilay Vaish |
| 2013-04-23 | x86: increment the stack pointer in lret inst | Christian Menard |
| 2013-03-11 | x86: implement some of the x87 instructions | Nilay Vaish |
| 2013-01-15 | x86: implements fsin, fcos instructions | Nilay Vaish |
| 2013-01-15 | x86: implements emms instruction | Nilay Vaish |
| 2013-01-15 | x86: implement fabs, fchs instructions | Nilay Vaish |
| 2012-12-30 | x86: implement x87 fp instruction fnstsw | Nilay Vaish |
| 2012-12-30 | x86: implement x87 fp instruction fsincos | Nilay Vaish |
| 2012-05-19 | x86 ISA: Implement the sse3 haddps instruction. | Marc Orr |
| 2012-04-29 | X86: Fix the IMUL_R_P_I macroop. | Gabe Black |
| 2012-01-09 | X86: Add memory fence to I/O instructions | Nilay Vaish |
| 2011-11-03 | x86: Add microop for fence | Nilay Vaish |
| 2011-05-06 | X86: Fix the Lldt instructions so they load the ldtr and not the tr. | Gabe Black |
| 2011-03-01 | X86: Mark IO reads and writes as non-speculative. | Gabe Black |
| 2011-02-07 | X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop. | Tim Harris |
| 2011-02-07 | X86: Fix JMP_FAR_I to unpack a far pointer correctly. | Tim Harris |
| 2011-02-07 | X86: Read the LDT/GDT at CPL0 when executing an iret. | Tim Harris |
| 2011-02-02 | X86: Replace the stupd microop with a store/update sequence. | Gabe Black |
| 2010-09-29 | X86: Fix the RIP relative versions of the BT, BTC, BTR, and BTS instructions. | Gabe Black |
