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path: root/src/arch/x86/isa/microops
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2007-07-21Implement rotate with carry microops.Gabe Black
--HG-- extra : convert_revision : 1d7ff6611e5b4766a5257c1e73681fabbe5f6d76
2007-07-20Fixed the distinction between far and near versions of jmp, call and ret. ↵Gabe Black
Implemented some shifts, rotates, and pushes. --HG-- extra : convert_revision : fcb06189ff213e82da16ac43231feb308cb3a285
2007-07-20Implement adc and sbb instructions and microops.Gabe Black
--HG-- extra : convert_revision : a2d3068c5b487f4fa7bf5c9cebba7753bc390bfa
2007-07-20Define and fill out a lot of different instructions and instruction ↵Gabe Black
versions. Added two of the shift microops. --HG-- extra : convert_revision : 0b76953dbb1dc3366242d4d209cccebde86bbe4e
2007-07-20Make load and store ops use the appropriate sized data access.Gabe Black
--HG-- extra : convert_revision : 6b808586fab10ca433ef04b062bf701b906634b9
2007-07-20Fix carry flag for subtracts, and clean up code slightly.Gabe Black
--HG-- extra : convert_revision : 668f5d5aeba888488b41284de6c72a0d055c4ef4
2007-07-19x86 fixesGabe Black
Make the emulation environment consider the rex prefix. Implement and hook in forms of j, jmp, cmp, syscall, movzx Added a format for an instruction to carry a call to the SE mode syscalls system Made memory instructions which refer to the rip do so directly Made the operand size overridable in the microassembly Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on Added an explicit "rax" operand for the syscall format Implemented syscall returns. --HG-- extra : convert_revision : ae84bd8c6a1d400906e17e8b8c4185f2ebd4c5f2
2007-07-18Make instructions that conditionally set registers set them to their old ↵Gabe Black
value if they don't actually execute. --HG-- extra : convert_revision : 36e63dd0c6ac1a3e1133c7985cf5507b83e9ee45
2007-07-18Make store microops actually store instead of load.Gabe Black
--HG-- extra : convert_revision : fe90f8adc96dd0e680cfa45e4c510a906046ae3d
2007-07-18Make the data size used by regops overridable in the microassembly.Gabe Black
--HG-- extra : convert_revision : 84d850aa5340c9d02d03502704b063215f6e2140
2007-07-18Add a generateDisassembly function to the MicroFault StaticInst.Gabe Black
--HG-- extra : convert_revision : 73811bf99b26fad413c9b84a54f44e3763ff1835
2007-07-17Make disassembled x86 register indices reflect their size.Gabe Black
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly. --HG-- extra : convert_revision : d495ac4f5756dc55a5f71953ff6963b3c030e6cb
2007-07-17Add in support for condition code flags.Gabe Black
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented. --HG-- extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f
2007-07-14Pull some hard coded base classes out of the isa description.Gabe Black
--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
2007-06-21Add in code that lays the ground work for setting flags.Gabe Black
--HG-- extra : convert_revision : e4fcb64d45804700a0ef34e8acf5615b66e2a527
2007-06-20Make memory instructions work better, add more macroop implementations, add ↵Gabe Black
an lea microop, move EmulEnv into it's own .cc and .hh. --HG-- extra : convert_revision : 1212b8463eab1c1dcba7182c487d1e9184cf9bea
2007-06-19More faithfulness to what instructions should work in what modes, and added ↵Gabe Black
the MOVSXD instruction. --HG-- extra : convert_revision : 38b9bf6cd4bdec6355b1158967c7d3562715cacd
2007-06-19Make instructions that are illegal in 64 bit mode not do the wrong thing in ↵Gabe Black
64 bit mode. Also add in more versions of PUSH and POP, and a version of near CALL. --HG-- extra : convert_revision : 7d8266cdfa54ac25610466b3533d3e9e5433297b
2007-06-19Renovate the "fault" microop implementation.Gabe Black
--HG-- extra : convert_revision : dc9d67dd5413f00f16d37cb2d0f8b0d10971e14a
2007-06-19Get rid of the immediate and displacement components of the EmulEnv struct ↵Gabe Black
and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops. --HG-- extra : convert_revision : 0686296ca8b72940d961ecc6051063bfda1e932d
2007-06-18Add in incomplete pick and merge functions which read and write pieces of ↵Gabe Black
registers, and fill out microcode disassembly. --HG-- extra : convert_revision : 56332b3999a9079b1bd305ee2826abdf593367e1
2007-06-14Fix limm.Gabe Black
--HG-- extra : convert_revision : ab76b11c2bb2f3abc0e7a84f7167d92d16ed074e
2007-06-13Move load/store microops into their own file. They still don't do anything, ↵Gabe Black
though. --HG-- extra : convert_revision : 251763c614b9056c3ca7a85ef92c416552da893f
2007-06-13Fix the immediate version of register operations, and get their name to show ↵Gabe Black
up correctly. --HG-- extra : convert_revision : 9fc36b99c9027e35f22983d5d1e22c940fa093de
2007-06-12Make microOp vs microop and macroOp vs macroop capitilization consistent.Gabe Black
src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. --HG-- extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
2007-06-08Fix the formatting on a comment.Gabe Black
--HG-- extra : convert_revision : 89636a7410dec54235416e3c16db98cc5eecf2b0
2007-06-08Big changes to use the new microcode assembler.Gabe Black
--HG-- extra : convert_revision : 7d1a43c5791a2e7e30533746da3dd7036a5b8799
2007-06-04Make limm (load immediate) microopGabe Black
--HG-- extra : convert_revision : f4883febd92cfade61c1a6a31fdb2d27296d9044
2007-06-04Reworking x86's microcode system. This is a work in progress, and X86 ↵Gabe Black
doesn't compile. src/arch/x86/isa/decoder/one_byte_opcodes.isa: src/arch/x86/isa/macroop.isa: src/arch/x86/isa/main.isa: src/arch/x86/isa/microasm.isa: src/arch/x86/isa/microops/base.isa: src/arch/x86/isa/microops/microops.isa: src/arch/x86/isa/operands.isa: src/arch/x86/isa/microops/regop.isa: src/arch/x86/isa/microops/specop.isa: Reworking x86's microcode system --HG-- extra : convert_revision : cab66be59ed758b192226af17eddd5a86aa190f3
2007-04-10Include the new GenFault microop.Gabe Black
--HG-- extra : convert_revision : 6c943329525d2a01f35ad5e56ff91505d5011d7b
2007-04-10Reworked x86 a bitGabe Black
--HG-- extra : convert_revision : def1a30e54b59c718c451a631a1be6f8e787e843
2007-04-06Consolidated the microcode assembler to help separate it from more ↵Gabe Black
x86-centric stuff. --HG-- extra : convert_revision : 5e7e8026e24ce44a3dac4a358e0c3e5560685958
2007-04-06Refactored the x86 isa description some more. There should be more ↵Gabe Black
seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere. --HG-- rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa extra : convert_revision : 5ab40eedf574fce438d9fe90e00a496dc95c8bcf
2007-04-04The process of going from an instruction definition to an instruction to be ↵Gabe Black
returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst. 1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter. 2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number. 3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM. 4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s. 5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it. In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though. src/arch/x86/isa/decoder/one_byte_opcodes.isa: src/arch/x86/isa/microasm.isa: src/arch/x86/isa/microops/microops.isa: src/arch/x86/isa/operands.isa: src/arch/x86/isa/microops/base.isa: Implemented polymorphic microops and changed around the microcode assembler syntax. --HG-- extra : convert_revision : e341f7b8ea9350a31e586a3d33250137e5954f43
2007-03-29Add code to generate register and immediate based integer op microop classes.Gabe Black
--HG-- extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
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