Age | Commit message (Collapse) | Author |
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--HG--
extra : convert_revision : a9d6d3568cd2c6a65df91bf56ee1e43523f04630
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extra : convert_revision : 153a055e888d8c47d59758a599dbd38f63008137
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extra : convert_revision : c551f51cdda46df99370363ed2d70916db8413eb
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--HG--
extra : convert_revision : 9d7ca286ba7709175fa75226320601acce4ced98
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--HG--
extra : convert_revision : 42f68010e6498aceb7ed25da278093e99150e4df
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--HG--
extra : convert_revision : 00a36a80a1945806aac9fa7d9d6a3906465dcad2
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Also some touch up for ruflag.
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extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
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extra : convert_revision : 566841577bf4a98cac0b65292fe0f7daf89a9203
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There is a fundemental flaw in how unaligned accesses are supported, but this
is still an improvement.
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extra : convert_revision : 1c20b524ac24cd4a812c876b067495ee6a7ae29f
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Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
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extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
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--HG--
extra : convert_revision : 073c6db0796cd2c11b8293b382b438a2a959b821
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"picked" register values.
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extra : convert_revision : 7b2c1be509478153ebf396841e4cbeccee3e03d1
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microops and instructions.
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extra : convert_revision : 5c56f6819ee07d936b388b3d1810a3b73db84f9c
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whether or not register indexes should be "folded".
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extra : convert_revision : 4b46e71ca91e480f6e1662b7f37b75240d6598e9
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The instructions now ask for the appropriate flags to be set, and the microops do the "right thing" with the CF and OF flags, namely zero them.
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extra : convert_revision : 85138a832f44c879bf8a11bd3a35b58be6272ef3
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--HG--
extra : convert_revision : c6057226b8ff8f272612a9d3bf7d1d9ba90c819b
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These functions take care of calling the thread contexts read and write functions with the right sized data type, and handle unaligned accesses.
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extra : convert_revision : b4b59ab2b22559333035185946bae3eab316c879
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The carry flag should be calculated using the -complement- of the second operand, not it's negation. The carry in which is part of computing the 2's complement may induce a carry, but if you've already caused the carry before you get the carry computing logic involved, it will miss it.
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extra : convert_revision : 318cf86929664fc52ed9e023606a9e892eba635c
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extra : convert_revision : 31c5d3fa8ef0d37494d0e35cef31be6056d5d93f
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extra : convert_revision : 1d7ff6611e5b4766a5257c1e73681fabbe5f6d76
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Implemented some shifts, rotates, and pushes.
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extra : convert_revision : fcb06189ff213e82da16ac43231feb308cb3a285
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extra : convert_revision : a2d3068c5b487f4fa7bf5c9cebba7753bc390bfa
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versions. Added two of the shift microops.
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extra : convert_revision : 0b76953dbb1dc3366242d4d209cccebde86bbe4e
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extra : convert_revision : 6b808586fab10ca433ef04b062bf701b906634b9
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extra : convert_revision : 668f5d5aeba888488b41284de6c72a0d055c4ef4
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Make the emulation environment consider the rex prefix.
Implement and hook in forms of j, jmp, cmp, syscall, movzx
Added a format for an instruction to carry a call to the SE mode syscalls system
Made memory instructions which refer to the rip do so directly
Made the operand size overridable in the microassembly
Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on
Added an explicit "rax" operand for the syscall format
Implemented syscall returns.
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extra : convert_revision : ae84bd8c6a1d400906e17e8b8c4185f2ebd4c5f2
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value if they don't actually execute.
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extra : convert_revision : 36e63dd0c6ac1a3e1133c7985cf5507b83e9ee45
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extra : convert_revision : fe90f8adc96dd0e680cfa45e4c510a906046ae3d
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extra : convert_revision : 84d850aa5340c9d02d03502704b063215f6e2140
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extra : convert_revision : 73811bf99b26fad413c9b84a54f44e3763ff1835
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This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
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extra : convert_revision : d495ac4f5756dc55a5f71953ff6963b3c030e6cb
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Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
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extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f
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--HG--
rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa
extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
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--HG--
extra : convert_revision : e4fcb64d45804700a0ef34e8acf5615b66e2a527
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an lea microop, move EmulEnv into it's own .cc and .hh.
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extra : convert_revision : 1212b8463eab1c1dcba7182c487d1e9184cf9bea
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the MOVSXD instruction.
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extra : convert_revision : 38b9bf6cd4bdec6355b1158967c7d3562715cacd
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64 bit mode. Also add in more versions of PUSH and POP, and a version of near CALL.
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extra : convert_revision : 7d8266cdfa54ac25610466b3533d3e9e5433297b
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extra : convert_revision : dc9d67dd5413f00f16d37cb2d0f8b0d10971e14a
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and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
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extra : convert_revision : 0686296ca8b72940d961ecc6051063bfda1e932d
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registers, and fill out microcode disassembly.
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extra : convert_revision : 56332b3999a9079b1bd305ee2826abdf593367e1
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--HG--
extra : convert_revision : ab76b11c2bb2f3abc0e7a84f7167d92d16ed074e
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though.
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extra : convert_revision : 251763c614b9056c3ca7a85ef92c416552da893f
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up correctly.
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extra : convert_revision : 9fc36b99c9027e35f22983d5d1e22c940fa093de
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src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
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extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
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--HG--
extra : convert_revision : 89636a7410dec54235416e3c16db98cc5eecf2b0
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--HG--
extra : convert_revision : 7d1a43c5791a2e7e30533746da3dd7036a5b8799
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--HG--
extra : convert_revision : f4883febd92cfade61c1a6a31fdb2d27296d9044
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doesn't compile.
src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/macroop.isa:
src/arch/x86/isa/main.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/base.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/regop.isa:
src/arch/x86/isa/microops/specop.isa:
Reworking x86's microcode system
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extra : convert_revision : cab66be59ed758b192226af17eddd5a86aa190f3
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--HG--
extra : convert_revision : 6c943329525d2a01f35ad5e56ff91505d5011d7b
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--HG--
extra : convert_revision : def1a30e54b59c718c451a631a1be6f8e787e843
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