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path: root/src/arch/x86/isa/operands.isa
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2009-08-07X86: Implement shift right/left double microops.Gabe Black
This is my best guess as far as what these should do. Other existing microops use implicit registers, mul1s and mul1u for instance, so this should be ok. The microop that loads the implicit DoubleBits register would fall into one of the microop slots for moving to/from special registers.
2009-07-17X86: Tame the wilds of def operands.Gabe Black
2009-02-25X86: Add microops for reading/writing debug registers.Gabe Black
2009-02-01X86: Fix some incorrect register widths.Gabe Black
2009-01-06X86: Hook in the M5 pseudo insts.Gabe Black
2008-10-12X86: Add wrval/rdval microops for reading significant miscregs.Gabe Black
2008-10-12X86: Implement CPUID with a magical function instead of microcode.Gabe Black
2008-06-12X86: Keep handy values like the operating mode in one register.Gabe Black
2008-06-12X86: Change what the microop chks does.Gabe Black
Instead of computing the segment descriptor address, this now checks if a selector value/descriptor are legal for a particular purpose.
2008-06-12X86: Add microops and supporting code to manipulate the whole rflags register.Gabe Black
2008-06-12X86: Add in some support for the tsc register.Gabe Black
2007-12-01X86: Reorganize segmentation and implement segment selector movs.Gabe Black
--HG-- extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
2007-12-01X86: Implement the lgdt instruction.Gabe Black
--HG-- extra : convert_revision : d1698a82df3c57cc9bbf8d5d190f271bfc7cb2e4
2007-12-01X86: Implement wrbase and wrlimit for loading pseudo descriptors.Gabe Black
--HG-- extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02
2007-12-01X86: Separate the effective seg base and the "hidden" seg base.Gabe Black
--HG-- extra : convert_revision : 5fcb8d94dbab7a7d6fe797277a5856903c885ad4
2007-11-13X86: Make microcode use presegmentation RIPs and the rest of m5 use post ↵Gabe Black
segmentation RIPS. --HG-- extra : convert_revision : d8cda7c8b9a2afb8a9d601b6d61529a96c5f87fe
2007-11-12X86: Implement the wrcr microop which writes a control register, and some ↵Gabe Black
control register work. --HG-- extra : convert_revision : 3e9daef9cdd0665c033420e5b4f981649e9908ab
2007-09-19X86: Move the fp microops to their own file with their own base classes in ↵Gabe Black
C++ and python. --HG-- extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
2007-09-19X86: Put in the foundation for x87 stack based fp registers.Gabe Black
--HG-- extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
2007-09-13X86: Total overhaul of the division instructions and microops.Gabe Black
--HG-- extra : convert_revision : 303ea45f69f7805361ad877fe6bb43fbc3dfd7a6
2007-09-06X86: Rework the multiplication microops so that they work like they would in ↵Gabe Black
the patent. --HG-- extra : convert_revision : 6fcf5dee440288d8bf92f6c5c2f97ef019975536
2007-08-29X86: Add operands to handle floating point registers.Gabe Black
--HG-- extra : convert_revision : 2e8289dbd3f5dda1221014d4ed0e9450f60de0cf
2007-08-29X86: Flesh out register indexing constants.Gabe Black
--HG-- extra : convert_revision : 56eedc076bbb7962c3976599a15ed93c7cb154c0
2007-08-07X86: Make a microcode branch microop.Gabe Black
Also some touch up for ruflag. --HG-- extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
2007-08-04X86: Start implementing segmentation support.Gabe Black
Make instructions observe segment prefixes, default segment rules, segment base addresses. Also fix some microcode and add sib and riprel "keywords" to the x86 specialization of the microassembler. --HG-- extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
2007-07-30X86: Take into account the regular registers and the microcode registers ↵Gabe Black
when decided whether or not to fold. --HG-- extra : convert_revision : 26feec984dec61799c4afb03a4503a53c35872c5
2007-07-30Make the register indices use the appropriate "fold" bit.Gabe Black
--HG-- extra : convert_revision : 89e15e2ef1f709f2c09238b78f94505ce8ef146d
2007-07-19x86 fixesGabe Black
Make the emulation environment consider the rex prefix. Implement and hook in forms of j, jmp, cmp, syscall, movzx Added a format for an instruction to carry a call to the SE mode syscalls system Made memory instructions which refer to the rip do so directly Made the operand size overridable in the microassembly Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on Added an explicit "rax" operand for the syscall format Implemented syscall returns. --HG-- extra : convert_revision : ae84bd8c6a1d400906e17e8b8c4185f2ebd4c5f2
2007-07-17Add in operand which holds the condition code bits of the flag register.Gabe Black
--HG-- extra : convert_revision : 416052f41fccc8286b3bdbe8d559512a761224f2
2007-06-19Get rid of the immediate and displacement components of the EmulEnv struct ↵Gabe Black
and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops. --HG-- extra : convert_revision : 0686296ca8b72940d961ecc6051063bfda1e932d
2007-06-04Reworking x86's microcode system. This is a work in progress, and X86 ↵Gabe Black
doesn't compile. src/arch/x86/isa/decoder/one_byte_opcodes.isa: src/arch/x86/isa/macroop.isa: src/arch/x86/isa/main.isa: src/arch/x86/isa/microasm.isa: src/arch/x86/isa/microops/base.isa: src/arch/x86/isa/microops/microops.isa: src/arch/x86/isa/operands.isa: src/arch/x86/isa/microops/regop.isa: src/arch/x86/isa/microops/specop.isa: Reworking x86's microcode system --HG-- extra : convert_revision : cab66be59ed758b192226af17eddd5a86aa190f3
2007-04-04The process of going from an instruction definition to an instruction to be ↵Gabe Black
returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst. 1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter. 2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number. 3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM. 4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s. 5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it. In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though. src/arch/x86/isa/decoder/one_byte_opcodes.isa: src/arch/x86/isa/microasm.isa: src/arch/x86/isa/microops/microops.isa: src/arch/x86/isa/operands.isa: src/arch/x86/isa/microops/base.isa: Implemented polymorphic microops and changed around the microcode assembler syntax. --HG-- extra : convert_revision : e341f7b8ea9350a31e586a3d33250137e5954f43
2007-03-29Add code to generate register and immediate based integer op microop classes.Gabe Black
--HG-- extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
2007-03-21Add a junk operand. With no operands, the parser breaks.Gabe Black
--HG-- extra : convert_revision : 7410fd3681ed3d9b1293d982ed5f3553a6c75f3f
2007-03-05Stub decoder. This is probably even farther from finished than it looks...Gabe Black
--HG-- extra : convert_revision : a39a158fec4560f6eb7a6987592c473677c0b1ba
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