Age | Commit message (Collapse) | Author |
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Implemented some shifts, rotates, and pushes.
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the decoder.
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register index from the opcode itself.
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versions. Added two of the shift microops.
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of signed multiplication.
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Make the emulation environment consider the rex prefix.
Implement and hook in forms of j, jmp, cmp, syscall, movzx
Added a format for an instruction to carry a call to the SE mode syscalls system
Made memory instructions which refer to the rip do so directly
Made the operand size overridable in the microassembly
Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on
Added an explicit "rax" operand for the syscall format
Implemented syscall returns.
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value if they don't actually execute.
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This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
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It still needs to zero the overflow and carry flags to be correct.
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Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
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could check.
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rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa
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