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2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-29X86: Fault on divide by zero instead of panicing.Gabe Black
2010-10-29X86: Make syscalls also serialize after.Gabe Black
2010-10-22X86: Make nop a regular, non-microcoded instruction.Gabe Black
Code in the CPUs that need a nop to carry a fault can't easily deal with a microcoded nop. This instruction format provides for one that isn't. --HG-- rename : src/arch/x86/isa/formats/syscall.isa => src/arch/x86/isa/formats/nop.isa
2010-10-22X86: Make syscall instructions non-speculative in SE.Gabe Black
2010-09-29X86: Fix the RIP relative versions of the BT, BTC, BTR, and BTS instructions.Gabe Black
2010-09-14X86: Make the halt microop non-speculative.Gabe Black
Executing this microop makes the CPU halt even if it was misspeculated.
2010-09-14X86: Make unrecognized instructions behave better in x86.Gabe Black
2010-08-23X86: Create a directory for files that define register indexes.Gabe Black
This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
2010-08-23X86: Get rid of the flagless microop constructor.Gabe Black
This will reduce clutter in the source and hopefully speed up compilation.
2010-08-23X86: Mark serializing macroops and regular instructions as such.Gabe Black
2010-08-23X86: Add a .serializing directive that makes a macroop serializing.Gabe Black
This directive really just tells the macroop to set IsSerializing and IsSerializeAfter on its final microop.
2010-08-23X86: Consolidate extra microop flags into one parameter.Gabe Black
This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor.
2010-08-22X86: Get rid of the unused getAllocator on the python base microop class.Gabe Black
This function is always overridden, and doesn't actually have the right signature.
2010-07-21Fix x86 XCHG macro-op to use locked micro-ops for all memory accessesTushar Krishna
2010-06-25X86: Fix div2 flag calculation.Gabe Black
2010-05-23copyright: Change HP copyright on x86 code to be more friendlyNathan Binkert
2010-05-12X86: Make the cvti2f microop sign extend its integer source correctly.Gabe Black
The code was using the wrong bit as the sign bit. Other similar bits of code seem to be correct.
2010-05-12X86: Actual change that fixes div. How did that happen?Gabe Black
2010-05-02X86: Sometimes CPUID depends on ecx, so pass that in.Gabe Black
2010-05-02X86: Finally fix a division corner case.Gabe Black
When doing an unsigned 64 bit division with a divisor that has its most significant bit set, the division code would spill a bit off of the end of a uint64_t trying to shift the dividend into position. This change adds code that handles that case specially by purposefully letting it spill and then going ahead assuming there was a 65th one bit.
2009-11-05compile: compile on 32 bit hardwareNathan Binkert
2009-12-19X86: Add a common named flag for signed media operations.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate high multiplies.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate scalar media instructions.Gabe Black
2009-11-11X86: add ULL to 1's being shifted in 64-bit valuesVince Weaver
Some of the micro-ops weren't casting 1 to ULL before shifting, which can cause problems. On the perl makerand input this caused some values to be negative that shouldn't have been. The casts are done as ULL(1) instead of 1ULL to match others in the m5 code base.
2009-11-10Merge with the head.Gabe Black
2009-11-10X86: Fix bugs in movd implementation.Vince Weaver
Unfortunately my implementation of the movd instruction had two bugs. In one case, when moving a 32-bit value into an xmm register, the lower half of the xmm register was not zero extended. The other case is that xmm was used instead of xmmlm as the source for a register move. My test case didn't notice this at first as it moved xmm0 to eax, which both have the same register number.
2009-11-10X86: Remove double-cast in Cvtf2i micro-opVince Weaver
This double cast led to rounding errors which caused some benchmarks to get the wrong values, most notably lucas which failed spectacularly due to CVTTSD2SI returning an off-by-one value. equake was also broken.
2009-11-08X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.Gabe Black
2009-11-04X86: Fix problem with movhps instructionVince Weaver
This problem is like the one fixed with movhpd a few weeks ago. A +8 displacement is used to access memory when there should be none. This fix is needed for the perlbmk spec2k benchmark to run.
2009-10-30X86: Add support for x86 psrldq and pslldq instructionsVince Weaver
These are complicated instructions and the micro-code might be suboptimal. This has been tested with some small sample programs (attached) The psrldq instruction is needed by various spec2k programs.
2009-10-30X86: Implement movd_Vo_Edp on X86Vince Weaver
This patch implements the movd_Vo_Edp series of instructions. It addresses various concerns by Gabe Black about which file the instruction belonged in, as well as supporting REX prefixed instructions properly. This instruction is needed for some of the spec2k benchmarks, most notably bzip2.
2009-10-30X86: Implement the X86 sse2 haddpd instructionVince Weaver
This patch implements the haddpd instruction. It fixes the problem in the previous version (pointed out by Gabe Black) where an incorrect result would happen if you issue the instruction with the same argument twice, i.e. "haddpd %xmm0,%xmm0" This instruction is used by many spec2k benchmarks.
2009-10-27X86: Replace "DISPLACEMENT" with disp in movhpd.Gabe Black
2009-10-27Fix problem with the x86 sse movhpd instruction.Vince Weaver
The movhpd instruction was writing to the wrong memory offset.
2009-10-21Implement X86 sse2 movdqu and movdqa instructionsVince Weaver
The movdqa instruction should enforce 16-byte alignment. This implementation does not do that. These instructions are needed for most of x86_64 spec2k to run.
2009-09-16X86: Sign extend the immediate of wripi like the register version.Gabe Black
2009-09-16X86: Make the imm8 member of immediate microops really 8 bits consistently.Gabe Black
2009-09-16X86: Fix checking the NT bit during an IRET.Gabe Black
2009-09-16X86: Fix setting the busy bit in the task descriptor in LTR.Gabe Black
2009-08-23Merge with head.Gabe Black
2009-08-23X86: Preserve the NO_ACCESS flag when giving CDA a specialized interface.Gabe Black
2009-08-21X86: fix some simple compile issuesNathan Binkert
static should not be used for constants that are not inside a class definition.
2009-08-20X86: Fix the decoding for and fill out FST and FSTP.Gabe Black
2009-08-20X86: Add microassembler symbols for floating point stack register operands.Gabe Black
2009-08-18X86: Decode the immediate byte opcode extension for 3dNow! instructions.Gabe Black
2009-08-18X86: Decode three byte opcodes.Gabe Black
2009-08-17X86: Double check the two byte portion of the decoder and fix bugs/clean up.Gabe Black
2009-08-17X86: Implement MOVNTI.Gabe Black