Age | Commit message (Collapse) | Author |
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C++ and python.
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rename : src/arch/x86/isa/insts/sse/__init__.py => src/arch/x86/isa/insts/simd128/__init__.py
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overflow flags like they're supposed to.
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the patent.
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to be with the other ones.
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This fixes a problem where interpreting arbitrary bits as floating point would
change what the value was. These values are legitimate because the fp
registers could be used to move around arbitrary data.
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it still needed.
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The new implementation uses metaclass, and gives a lot more precise control
with a lot less verbosity. The flags/no flags reg/imm variants are all handled
by the same python class now which supplies a constructor to the right C++
class based on context.
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This includes the most of the SSE stuff, but not some of the "groups" of
instructions.
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machine returns.
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The labels on these lines will be associated with whatever the next microop
is.
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The flag mechanism for microops needs to be fleshd out a little more to allow
for custom flag calculation methods for certain microops. Shift is an example
where the rules for calculating OF and CF are unique.
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Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.
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repne prefixes.
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Also some touch up for ruflag.
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There is a fundemental flaw in how unaligned accesses are supported, but this
is still an improvement.
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REX prefix.
The only cases where this was the correct behavior are now handled with the
"B" operand type, and doing things this way was breaking some instructions,
notably a shift.
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Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
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