gem5 - gem5

Age	Commit message (Collapse)	Author
2014-11-23	mem: Page Table map api modification	Alexandru Dutu
	This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes.
2013-08-07	x86: add tlb checkpointing	Nilay Vaish
	This patch adds checkpointing support to x86 tlb. It upgrades the cpt_upgrader.py script so that previously created checkpoints can be updated. It moves the checkpoint version to 6.
2012-07-10	x86: logSize and lruSeq are now optional ckpt params	Brad Beckmann

2012-04-14	X86: Use the AddrTrie class to implement the TLB.	Gabe Black
	This change also adjusts the TlbEntry class so that it stores the number of address bits wide a page is rather than its size in bytes. In other words, instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K, but it's a little harder going the other way.
2011-02-06	x86: Add checkpointing capability to arch components	Joel Hestness
	Add checkpointing capability to the x86 interrupt device and the TLBs
2010-05-23	copyright: Change HP copyright on x86 code to be more friendly	Nathan Binkert

2007-10-25	TLB: Fix serialization issues with the tlb entries and make the page table ↵	Gabe Black
	store the process, not the system. --HG-- extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8
2007-10-02	X86: Start implementing the x86 tlb which will handle segmentation ↵	Gabe Black
	permission and limit checks and paging. --HG-- extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af