Age | Commit message (Collapse) | Author |
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This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
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This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
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--HG--
rename : src/sim/host.hh => src/base/types.hh
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been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.
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--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
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store the process, not the system.
--HG--
extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8
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permission and limit checks and paging.
--HG--
extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af
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--HG--
extra : convert_revision : 94f3f19eb91b7f54918640b7605008eb1fe75fc7
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