gem5 - gem5

Age	Commit message (Collapse)	Author
2016-01-17	arch: get rid of unused LargestRead typedef	Steve Reinhardt

2015-07-28	revert 5af8f40d8f2c	Nilay Vaish

2015-07-26	cpu: implements vector registers	Nilay Vaish
	This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
2013-10-15	arch/x86: add support for explicit CC register file	Yasuko Eckert
	Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch.
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
	Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
	Make these names more meaningful. Specifically, made these substitutions: s/FP_Base_DepTag/FP_Reg_Base/g; s/Ctrl_Base_DepTag/Misc_Reg_Base/g; s/Max_DepTag/Max_Reg_Index/g;
2013-10-15	isa: clean up register constants	Steve Reinhardt
	Clean up and add some consistency to the *_Base_DepTag constants as well as some related register constants: - Get rid of NumMiscArchRegs, TotalArchRegs, and TotalDataRegs since they're never used and not always defined - Set FP_Base_DepTag = NumIntRegs when possible (i.e., every case except x86) - Set Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs (this was true before, but wasn't always expressed that way) - Drastically reduce the number of arbitrary constants appearing in these calculations
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
	DynInst is extremely large the hope is that this re-organization will put the most used members close to each other.
2012-04-23	ISA: Put parser generated files in a "generated" directory.	Gabe Black
	This is to avoid collision with non-generated files.
2011-04-15	includes: sort all includes	Nathan Binkert

2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
	Ran all the source files through 'perl -pi' with this script: s\|\s(};?\s)?/\\s(end\s)?namespace\s(\S+)\s\/(\s})?\|} // namespace $3\|; s\|\s};?\s//\s(end\s)?namespace\s(\S+)\s\|} // namespace $2\n\|; s\|\s};?\s//\s(\S+)\snamespace\s\|} // namespace $1\n\|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2010-08-25	ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)	Min Kyu Jeong
	When decoding a srs instruction, invalid mode encoding returns invalid instruction. This can happen when garbage instructions are fetched from mispredicted path
2010-08-23	X86: Create a directory for files that define register indexes.	Gabe Black
	This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
2010-05-23	copyright: Change HP copyright on x86 code to be more friendly	Nathan Binkert

2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
	This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh