gem5 - gem5

Age	Commit message (Collapse)	Author
2014-11-23	x86: Segment initialization to support KvmCPU in SE	Alexandru Dutu
	This patch sets up low and high privilege code and data segments and places them in the following order: cs low, ds low, ds, cs, in the GDT. Additionally, a syscall and page fault handler for KvmCPU in SE mode are defined. The order of the segment selectors in GDT is required in this manner for interrupt handling to work properly. Segment initialization is done for all the thread contexts.
2013-10-15	arch/x86: add support for explicit CC register file	Yasuko Eckert
	Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch.
2013-09-18	x86: Expose the raw hash map of MSRs	Andreas Sandberg
	This patch allows the KVM CPU module to initialize it's MSRs by enumerating the MSRs in the gem5 x86 implementation.
2013-01-15	x86: implement fabs, fchs instructions	Nilay Vaish

2012-09-11	x86: Add a separate register for D flag bit	Nilay Vaish
	The D flag bit is part of the cc flag bit register currently. But since it is not being used any where in the implementation, it creates an unnecessary dependency. Hence, it is being moved to a separate register.
2012-05-22	X86: Split Condition Code register	Nilay Vaish
	This patch moves the ECF and EZF bits to individual registers (ecfBit and ezfBit) and the CF and OF bits to cfofFlag registers. This is being done so as to lower the read after write dependencies on the the condition code register. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Note that this is only one part of the solution for lowering the dependencies. The other part will check whether or not the condition code register needs to be actually read. This would be done through a separate patch.
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
	This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
2011-09-23	X86: Move the MSR lookup table out of the TLB and into its own file.	Gabe Black
	Translating MSR addresses into MSR register indices took a lot of space in the TLB source and made looking around in that file awkward. This change moves the lookup into its own file to get it out of the way. It also changes it from a switch statement to a hash map which should hopefully be a little more efficient.
2010-08-23	X86: Create a directory for files that define register indexes.	Gabe Black
	This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh