| Age | Commit message (Expand) | Author |
|---|
| 2017-07-17 | x86: Add stats to X86 TLB | Swapnil Haria |
| 2017-02-23 | x86: remove redundant condition check in tlb code | Brandon Potter |
| 2016-11-09 | style: [patch 3/22] reduce include dependencies in some headers | Brandon Potter |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-09-13 | x86: Force strict ordering for memory mapped m5ops | Michael LeBeane |
| 2016-08-15 | cpu, arch: fix the type used for the request flags | Nikos Nikoleris |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2014-11-23 | kvm, x86: Adding support for SE mode execution | Alexandru Dutu |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2013-10-15 | mem: Use a flag instead of address bit 63 for generic IPRs | Andreas Sandberg |
| 2013-09-30 | x86: Add support for m5ops through a memory mapped interface | Andreas Sandberg |
| 2013-08-07 | x86: add tlb checkpointing | Nilay Vaish |
| 2013-06-03 | arch: Create a method to finalize physical addresses | Andreas Sandberg |
| 2013-01-07 | arch: Add support for invalidating TLBs when draining | Andreas Sandberg |
| 2012-10-15 | Port: Add protocol-agnostic ports in the port hierarchy | Andreas Hansson |
| 2012-06-07 | X86 TLB: Add a missing = sign | Nilay Vaish |
| 2012-06-07 | X86 TLB: Fix for gcc 4.4.3 | Jayneel Gandhi |
| 2012-05-28 | X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB. | Gabe Black |
| 2012-05-27 | X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode. | Gabe Black |
| 2012-04-24 | X86: Clear out duplicate TLB entries when adding a new one. | Gabe Black |
| 2012-04-14 | X86: Use the AddrTrie class to implement the TLB. | Gabe Black |
| 2012-03-31 | X86: Fix address size handling so real mode works properly. | Gabe Black |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-03-19 | gcc: Clean-up of non-C++0x compliant code, first steps | Andreas Hansson |
| 2012-03-09 | CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU | Geoffrey Blake |
| 2012-03-01 | x86: Fix x86 TLB and Walker | Nilay Vaish |
| 2012-01-07 | Another merge with the main repository. | Gabe Black |
| 2012-01-05 | X86 TLB: Move a DPRINTF to its correct place | Nilay Vaish |
| 2011-10-30 | X86: Get rid of more uses of FULL_SYSTEM. | Gabe Black |
| 2011-10-30 | SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. | Gabe Black |
| 2011-10-13 | X86: Turn on the page table walker in SE mode. | Gabe Black |
| 2011-09-23 | X86: Move the MSR lookup table out of the TLB and into its own file. | Gabe Black |
| 2011-09-09 | Stack: Tidy up some comments, a warning, and make stack extension consistent. | Gabe Black |
| 2011-09-05 | X86,TLB: Make sure the "delayedResponse" variable is always set. | Gabe Black |
| 2011-09-02 | TLB: comments and a helpful warning. | Lisa Hsu |
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2011-03-01 | Spelling: Fix the a spelling error by changing mmaped to mmapped. | Gabe Black |
| 2011-02-27 | X86: If PCI config space is disabled, pass through to regular IO addresses. | Gabe Black |
| 2011-02-07 | X86: Obey the wp bit of CR0. | Tim Harris |
| 2011-02-06 | x86: Timing support for pagetable walker | Joel Hestness |
| 2011-01-03 | Make commenting on close namespace brackets consistent. | Steve Reinhardt |
| 2010-11-23 | X86: Obey the PCD (cache disable) bit in the page tables. | Gabe Black |
| 2010-11-22 | X86: Mark IO space accesses as uncachable. | Gabe Black |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-08-23 | X86: Create a directory for files that define register indexes. | Gabe Black |
| 2010-08-23 | X86: Make the TLB fault instead of panic when something is unmapped in SE mode. | Gabe Black |
| 2010-05-23 | copyright: Change HP copyright on x86 code to be more friendly | Nathan Binkert |
| 2009-11-08 | X86: Don't panic on faults on prefetches in SE mode. | Gabe Black |
