| Age | Commit message (Expand) | Author |
|---|
| 2011-09-23 | X86: Move the MSR lookup table out of the TLB and into its own file. | Gabe Black |
| 2011-09-09 | Stack: Tidy up some comments, a warning, and make stack extension consistent. | Gabe Black |
| 2011-09-05 | X86,TLB: Make sure the "delayedResponse" variable is always set. | Gabe Black |
| 2011-09-02 | TLB: comments and a helpful warning. | Lisa Hsu |
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2011-03-01 | Spelling: Fix the a spelling error by changing mmaped to mmapped. | Gabe Black |
| 2011-02-27 | X86: If PCI config space is disabled, pass through to regular IO addresses. | Gabe Black |
| 2011-02-07 | X86: Obey the wp bit of CR0. | Tim Harris |
| 2011-02-06 | x86: Timing support for pagetable walker | Joel Hestness |
| 2011-01-03 | Make commenting on close namespace brackets consistent. | Steve Reinhardt |
| 2010-11-23 | X86: Obey the PCD (cache disable) bit in the page tables. | Gabe Black |
| 2010-11-22 | X86: Mark IO space accesses as uncachable. | Gabe Black |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-08-23 | X86: Create a directory for files that define register indexes. | Gabe Black |
| 2010-08-23 | X86: Make the TLB fault instead of panic when something is unmapped in SE mode. | Gabe Black |
| 2010-05-23 | copyright: Change HP copyright on x86 code to be more friendly | Nathan Binkert |
| 2009-11-08 | X86: Don't panic on faults on prefetches in SE mode. | Gabe Black |
| 2009-11-08 | X86: Explain what really didn't work with unmapped addresses in SE mode. | Gabe Black |
| 2009-08-01 | Clean up some inconsistencies with Request flags. | Steve Reinhardt |
| 2009-07-08 | Registers: Eliminate the ISA defined floating point register file. | Gabe Black |
| 2009-07-08 | Registers: Add an ISA object which replaces the MiscRegFile. | Gabe Black |
| 2009-04-26 | X86: Split out the internal memory space from the regular translate() and pre... | Gabe Black |
| 2009-04-23 | X86: Put the StoreCheck flag with the others, and don't collide with other fl... | Gabe Black |
| 2009-04-19 | X86: Fix how the TLB handles the storecheck flag. | Gabe Black |
| 2009-04-19 | X86: Some segment selectors can be used when "NULL". | Gabe Black |
| 2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black |
| 2009-02-27 | quell gcc 4.3 warning | Nathan Binkert |
| 2009-02-27 | X86: Fix segment limit checks. | Gabe Black |
| 2009-02-25 | X86: Actually check page protections. | Gabe Black |
| 2009-02-25 | X86: Add a flag to force memory accesses to happen at CPL 0. | Gabe Black |
| 2009-02-25 | X86: Make the X86 TLB take advantage of delayed translations, and get rid of ... | Gabe Black |
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert t... | Gabe Black |
| 2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black |
| 2009-02-23 | X86: Pass whether an access was a read/write/fetch so faults can behave accor... | Gabe Black |
| 2009-02-01 | X86: Compute PCI config addresses correctly. | Gabe Black |
| 2008-11-10 | mem: update stuff for changes to Packet and Request | Nathan Binkert |
| 2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu |
| 2008-11-02 | make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered | Lisa Hsu |
| 2008-10-12 | X86: Make the local APIC accessible through the memory system directly, and m... | Gabe Black |
| 2008-10-12 | Turn Interrupts objects into SimObjects. Also, move local APIC state into x86... | Gabe Black |
| 2008-06-12 | X86: Rename the divide count register to divide configuration. | Gabe Black |
| 2008-06-12 | X86: Change how segment loading is performed. | Gabe Black |
| 2008-06-12 | X86: In non 64bit mode, throw a fault when a NULL segment is accessed. | Gabe Black |
| 2008-06-12 | X86: Have all 8 machine check registers since the kernel assumes they're there. | Gabe Black |
| 2008-06-12 | X86: Bypass unaligned access support for register addressed MSRs. | Gabe Black |
| 2008-06-12 | X86: Remove enforcement of APIC register access alignment. Panic if more than... | Gabe Black |
| 2008-03-01 | X86: Don't map the local APIC into the physical address space in SE mode. | Gabe Black |
| 2008-02-26 | X86: Put in initial implementation of the local APIC. | Gabe Black |
