Age | Commit message (Collapse) | Author |
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--HG--
extra : convert_revision : 659786bf6489ab6151e47fbf1f4c0a723262fce2
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--HG--
extra : convert_revision : 4c53be6568134d65e57f5411df986fd9a89e82c9
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Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
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--HG--
extra : convert_revision : f1bbd5165a7415d0daf27660575d30c41510f531
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--HG--
extra : convert_revision : 7ff4998b3249ccfe86ae9cbcc63fb910683707f5
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--HG--
extra : convert_revision : 2ef8ee71999f36b09270ba9526c2846beda65051
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--HG--
extra : convert_revision : 8d55ca9645ee4e357b7f4595435542eb72490331
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an lea microop, move EmulEnv into it's own .cc and .hh.
--HG--
extra : convert_revision : 1212b8463eab1c1dcba7182c487d1e9184cf9bea
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and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
--HG--
extra : convert_revision : 0686296ca8b72940d961ecc6051063bfda1e932d
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--HG--
extra : convert_revision : 7fc6567ab3d35c06901e6c8a0435f7cab819e17e
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--HG--
extra : convert_revision : f8907ef5ef77e050eeb00d895263b49da4a9b6e9
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sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
--HG--
extra : convert_revision : e59b747198cc79d50045bd2dc45b2e2b97bbffcc
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and a real hash function.
--HG--
extra : convert_revision : 30f29a36f6ab44e67e62aaf81b685fbe1267c746
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what bits decode is done on to reflect where clumps of instructions are.
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extra : convert_revision : 8768676eac25e6a4f0dc50ce2dc576bdcdd6e025
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byte opcodes.
--HG--
extra : convert_revision : 4c79bff2592a668e1154916875f019ecafe67022
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adding predecoding functionality to x86.
src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
--HG--
extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
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Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
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extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
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--HG--
extra : convert_revision : 5570a595b9adbe9c35f9b4f8dd3b50533b5beb97
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--HG--
extra : convert_revision : 712480fef36bf7a34c2c0b8d19dd82689eb78a1d
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nonsensical for x86.
--HG--
extra : convert_revision : 2f7845db6d65b353985b474f7012cfbbaece6a39
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--HG--
extra : convert_revision : 438eb74f14e6ea60bab5012110f3946c9213786e
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