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2009-02-01X86: Set/correct some default values for x86 parameters.Gabe Black
2009-01-25X86: Implement the xadd instruction.Gabe Black
2009-01-25X86: Implement the bswap instruction.Gabe Black
2009-01-25X86: Fix a bug in the iret microcode.Gabe Black
2009-01-25X86: Make the interrupt object wake up the CPU when something becomes pending.Gabe Black
2009-01-25CPU: Add a setCPU function to the interrupt objects.Gabe Black
2009-01-19tracing: Add help strings for some of the trace flagsNathan Binkert
2009-01-13SCons: centralize the Dir() workaround for newer versions of scons.Nathan Binkert
Scons bug id: 2006 M5 Bug id: 308
2009-01-06X86: Hook in the M5 pseudo insts.Gabe Black
2009-01-06X86: Autogenerate macroop generateDisassemble function.Gabe Black
2009-01-06X86: Move the function that prints memory args into the inst base class.Gabe Black
2009-01-06X86: Move the macroop class out of the isa description into C++.Gabe Black
2009-01-06X86: Change indentation on microop disassembly.Gabe Black
2008-12-07imported patch aux-fix.patchLisa Hsu
2008-12-06X86: Add add_entry back in.Gabe Black
2008-12-04This patch pulls out the auxiliary vector struct from individual ISALisa Hsu
LiveProcesses to the base LiveProcess definition so anyone can use them.
2008-11-15syscalls: fix latent brk/obreak bug.Steve Reinhardt
Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process.
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-11-09X86: Fix completeAcc get call.Gabe Black
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-11-02Make it so that all thread contexts are registered with the System, even inLisa Hsu
SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration.
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. ↵Ali Saidi
Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change.
2008-10-16get rid of local variable that's only used in an assert so fast compilesNathan Binkert
2008-10-12X86: Set the delayed commit flag in x86 microops appropriately.Gabe Black
2008-10-12X86: Make the local APIC timer event generate an interrupt.Gabe Black
2008-10-12X86: Implement the EOI register in the local APIC.Gabe Black
2008-10-12X86: Add some DPRINTFs to the local APIC.Gabe Black
2008-10-12X86: Fix the segment setting code in IRET, and make it restore the flags.Gabe Black
2008-10-12X86: Panic when an unimplemented fault is invoked, rather than spinning foreverGabe Black
2008-10-12X86: Implement the swapgs instruction.Gabe Black
2008-10-12X86: Add wrval/rdval microops for reading significant miscregs.Gabe Black
2008-10-12X86: Make the x86 interrupt fault kick off the interrupt microcode.Gabe Black
2008-10-12X86: Implement entering an interrupt in microcode.Gabe Black
2008-10-12X86: Make sure register microops set fault rather than returning one.Gabe Black
2008-10-12X86: Implement an wrdh microop which loads bases/offsets from 16 byte ↵Gabe Black
descriptors.
2008-10-12X86: Implement local labels for the ROM that actually refer into the ROM.Gabe Black
2008-10-12X86: Implement the chks check of interrupt gate target code segments.Gabe Black
2008-10-12X86: Add a check type for interrupt gates.Gabe Black
2008-10-12X86: Fix chks checking the submode for stack segments.Gabe Black
2008-10-12X86: Let segment manipulation microops be conditional.Gabe Black
2008-10-12X86: Let the microassembler know about the microcode only H segment.Gabe Black
2008-10-12X86: Fix the rdbase microopGabe Black
2008-10-12Get rid of old RegContext code.Gabe Black
2008-10-12X86: Create a handy way to access labels from the ROM in microcode.Gabe Black
2008-10-12X86: Make X86's microcode ROM actually do something.Gabe Black
2008-10-12CPU: Create a microcode ROM object in the CPU which is defined by the ISA.Gabe Black
2008-10-12X86: Create an eret microop which returns from ROM to combinational decoding.Gabe Black
2008-10-12X86: Make Br never report itself as the last microop.Gabe Black