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AgeCommit message (Expand)Author
2008-10-12X86: Implement the chks check of interrupt gate target code segments.Gabe Black
2008-10-12X86: Add a check type for interrupt gates.Gabe Black
2008-10-12X86: Fix chks checking the submode for stack segments.Gabe Black
2008-10-12X86: Let segment manipulation microops be conditional.Gabe Black
2008-10-12X86: Let the microassembler know about the microcode only H segment.Gabe Black
2008-10-12X86: Fix the rdbase microopGabe Black
2008-10-12Get rid of old RegContext code.Gabe Black
2008-10-12X86: Create a handy way to access labels from the ROM in microcode.Gabe Black
2008-10-12X86: Make X86's microcode ROM actually do something.Gabe Black
2008-10-12CPU: Create a microcode ROM object in the CPU which is defined by the ISA.Gabe Black
2008-10-12X86: Create an eret microop which returns from ROM to combinational decoding.Gabe Black
2008-10-12X86: Make Br never report itself as the last microop.Gabe Black
2008-10-12X86: Create a SeqOp class of microops and make Br one of them.Gabe Black
2008-10-12X86: Implement CPUID with a magical function instead of microcode.Gabe Black
2008-10-12X86: Fix the ordering of special physical address ranges.Gabe Black
2008-10-12X86: Make the local APIC process interrupts and send them to the CPU.Gabe Black
2008-10-12X86: Make the local APIC handle interrupt messages from the IO APIC.Gabe Black
2008-10-12X86: Make the bases for x86 fault class public.Gabe Black
2008-10-12X86: Make APICs communicate through the memory system.Gabe Black
2008-10-12X86: Add a LocalApic trace flag.Gabe Black
2008-10-12X86: Make the local APIC accessible through the memory system directly, and m...Gabe Black
2008-10-12Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...Gabe Black
2008-10-12CPU: Eliminate the get_vec function.Gabe Black
2008-10-11X86: Add an Intel MP table to the simulation.Gabe Black
2008-10-10TLB: Make all tlbs derive from a common base class in both python and C++.Gabe Black
2008-10-10X86: Create SimObjects in python and C++ to represent the ACPI system descrip...Gabe Black
2008-10-10X86: Create SimObjects in python and C++ to represent the Intel MP tables.Gabe Black
2008-10-10automergeNathan Binkert
2008-10-10misc: remove #include <cassert> from misc.hh since not everyone needs it.Nathan Binkert
2008-10-10X86: Turn SMBios structures into simobjects.Gabe Black
2008-10-10X86: Add a couple comments to the bios SConscriptGabe Black
2008-10-10X86: Move the smbios objects into a folder for BIOS objects.Gabe Black
2008-10-09SimObjects: Clean up handling of C++ namespaces.Nathan Binkert
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-10-09X86: Fix the debugging microops. The debug functions can't handle a string ob...Gabe Black
2008-10-09X86: Make far ret modify CS instead of some random selector.Gabe Black
2008-09-27gcc: Add extra parens to quell warnings.Nathan Binkert
2008-09-27arch: TheISA shouldn't really ever be used in the arch directory.Nathan Binkert
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-09-03X86: Fix the microcode for sign/zero extending moves that use high byte regis...Gabe Black
2008-08-03X86: Make hint nops consume their modrm byte.Gabe Black
2008-07-01Remove delVirtPort() and make getVirtPort() only return cached version.Ali Saidi
2008-06-14Fix various SWIG warningsNathan Binkert
2008-06-12X86: Make the cpuid processor identifier return a real string.Gabe Black
2008-06-12X86: Make the e820 table manually or automatically configurable from python.Gabe Black
2008-06-12X86: Make the disassembly for halt conform with the other microops.Gabe Black
2008-06-12X86: Implement and hook up STI and CLI instructions.Gabe Black
2008-06-12X86: Add an event for the apic timer timeout. It doesn't get used yet.Gabe Black
2008-06-12X86: Rename the divide count register to divide configuration.Gabe Black
2008-06-12X86: Make the apic isr and irr work.Gabe Black
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