| Age | Commit message (Expand) | Author |
|---|
| 2015-07-17 | x86: decode instructions with vex prefix | Nilay Vaish |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-07-04 | x86: Adjust the size of the values written to the x87 misc registers | Nikos Nikoleris |
| 2015-05-15 | misc: Appease gcc 5.1 | Andreas Hansson |
| 2015-05-05 | syscall_emul: fix warn_once behavior | Steve Reinhardt |
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2015-05-05 | arch, cpu: Do not forward snoops to table walker | Andreas Hansson |
| 2015-04-29 | x86: change divide-by-zero fault to divide-error | Nilay Vaish |
| 2015-04-24 | misc: Appease gcc 5.1 without moving GDB_REG_BYTES | Andreas Hansson |
| 2015-04-23 | misc: Appease gcc 5.1 | Andreas Hansson |
| 2015-04-22 | syscall_emul: implement clock_gettime system call | Brandon Potter |
| 2015-04-22 | syscall_emul: update x86 syscall table | Monir Mozumder |
| 2015-04-13 | x86: implements x87 mult/div instructions | Nilay Vaish |
| 2015-04-03 | x86: fix debug trace output for mwait | Lena Olson |
| 2015-03-23 | mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW | Steve Reinhardt |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
| 2015-02-11 | mem: Clarification of packet crossbar timings | Marco Balboni |
| 2015-02-11 | sim: Move the BaseTLB to src/arch/generic/ | Andreas Sandberg |
| 2015-01-25 | cpu: Put all CPU instruction tracers in a single file | Ali Saidi |
| 2015-01-22 | mem: Remove unused Packet src and dest fields | Andreas Hansson |
| 2015-01-22 | x86: Delay X86 table walk on receiving walker response | Andreas Hansson |
| 2015-01-10 | x86 : fxsave and fxrestore missing template code | Emilio Castillo |
| 2015-01-06 | x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield. | Gabe Black |
| 2015-01-06 | cpuid, x86: Revert "Enabling more features in CPUid" | Gabe Black |
| 2015-01-03 | x86: implements the simd128 ADDSUBPD instruction | Maxime Martinasso |
| 2014-12-05 | misc: Generalize GDB single stepping. | Gabe Black |
| 2014-12-05 | x86: Implement a remote GDB stub. | Gabe Black |
| 2014-12-04 | x86: Rework opcode parsing to support 3 byte opcodes properly. | Gabe Black |
| 2014-12-02 | x86: Clean up style in process.cc. | Gabe Black |
| 2014-11-23 | mem: Page Table map api modification | Alexandru Dutu |
| 2014-11-23 | x86: Segment initialization to support KvmCPU in SE | Alexandru Dutu |
| 2014-11-23 | kvm, x86: Adding support for SE mode execution | Alexandru Dutu |
| 2014-11-23 | cpuid, x86: Enabling more features in CPUid | Alexandru Dutu |
| 2014-11-17 | x86: Fix setting segment bases in real mode. | Gabe Black |
| 2014-11-17 | x86: Fix some bugs in the real mode far jmp instruction. | Gabe Black |
| 2014-11-17 | x86: APIC: Only set deliveryStatus if our IPI is going somewhere. | Gabe Black |
| 2014-11-17 | x86: APIC: Fix the getRegArrayBit function. | Gabe Black |
| 2014-11-16 | x86: Fix the CPUID Long Mode Address Size function. | Gabe Black |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-22 | sim: revert 6709bbcf564d | Nilay Vaish |
| 2014-10-20 | x86: Fixes to avoid LTO warnings | Andreas Hansson |
| 2014-10-20 | sim: implement getdents/getdents64 in user mode | Michael Adler |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2014-10-16 | arch,x86,mem: Dynamically determine the ISA for Ruby store check | Andreas Hansson |
| 2014-06-13 | x86: add LongModeAddressSize function to cpuid | Jiuyue Ma |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-09-20 | mem: Rename Bus to XBar to better reflect its behaviour | Andreas Hansson |
| 2014-09-03 | x86: Flag instructions that call suspend as IsQuiesce | Mitch Hayenga |
