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path: root/src/arch/x86
AgeCommit message (Expand)Author
2012-08-06syscall emulation: Clean up ioctl handling, and implement for x86.Marc Orr
2012-07-22X86 CPUID: Return false if unknown processor familyNilay Vaish
2012-07-11x86: added page size in bytes tlb entry functionBrad Beckmann
2012-07-10syscall emulation: Add the futex system call.Marc Orr
2012-07-10x86: logSize and lruSeq are now optional ckpt paramsBrad Beckmann
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-06-07X86 TLB: Add a missing = signNilay Vaish
2012-06-07X86 TLB: Fix for gcc 4.4.3Jayneel Gandhi
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
2012-06-04X86: Ensure that the CPUID instruction always writes its outputs.Gabe Black
2012-06-04X86: Ensure that the decoder's internal ExtMachInst is completely initialized.Gabe Black
2012-05-28X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.Gabe Black
2012-05-27X86: Move the GDT down to where it can be accessed in 32 bit mode.Gabe Black
2012-05-27X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.Gabe Black
2012-05-26ISA,CPU: Generalize and split out the components of the decode cache.Gabe Black
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-05-22X86: Split Condition Code registerNilay Vaish
2012-05-19x86 ISA: Implement the sse3 haddps instruction.Marc Orr
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-29X86: Fix the IMUL_R_P_I macroop.Gabe Black
2012-04-29X86: Fix up the open system call's flags.Vince Weaver
2012-04-29X86: Make gem5 ignore a bunch of syscalls.Vince Weaver
2012-04-24X86: Clear out duplicate TLB entries when adding a new one.Gabe Black
2012-04-23ISA: Put parser generated files in a "generated" directory.Gabe Black
2012-04-21X86: Report an error if there's no kernel object, don't blindly use it.Gabe Black
2012-04-15X86: Fix a tiny typo in the load/store microop constructor.Gabe Black
2012-04-14X86: Use the AddrTrie class to implement the TLB.Gabe Black
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
2012-03-31X86: Fix address size handling so real mode works properly.Gabe Black
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-19clang: Fix recently introduced clang compilation errorsAndreas Hansson
2012-03-09CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPUGeoffrey Blake
2012-03-01x86: Fix x86 TLB and WalkerNilay Vaish
2012-02-26X86: Use the M5PanicFault fault in execute methods instead of calling panic.Gabe Black
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12X86: open flags: Another patch from Vince WeaverGabe Black
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-29Implement Ali's review feedback.Gabe Black