| Age | Commit message (Expand) | Author |
|---|
| 2019-05-29 | sim-se: add a release parameter to Process.py | Ciro Santilli |
| 2019-05-29 | arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods. | Gabe Black |
| 2019-05-22 | sim-se: remove comment for code that moved | Brandon Potter |
| 2019-05-21 | sim-se: change syscall function signature | Brandon Potter |
| 2019-05-20 | x86: Add an object file loader for linux. | Gabe Black |
| 2019-05-07 | x86: Mark translation as delayed in case of a hw page table walk | Gabor Dozsa |
| 2019-05-03 | sim-se: add eventfd system call | Brandon Potter |
| 2019-04-30 | arch: Stop using TheISA within the ISAs. | Gabe Black |
| 2019-04-30 | x86: Get rid of some unnecessary TheISA-es in x86. | Gabe Black |
| 2019-04-28 | arch, sim: Simplify the AuxVector type. | Gabe Black |
| 2019-04-28 | mem: Remove the ISA specialized versions of port proxy's read/write. | Gabe Black |
| 2019-04-28 | mem: Minimize the use of MemObject. | Gabe Black |
| 2019-04-25 | x86: Refactor the ProcessInfo constructor. | Gabe Black |
| 2019-04-25 | x86: Fix some style issues in stacktrace.cc. | Gabe Black |
| 2019-04-22 | sim-se: Enhance clone for X86KvmCPU | Alexandru Dutu |
| 2019-03-19 | arch, cpu, dev, gpu, mem, sim, python: start using getPort. | Gabe Black |
| 2019-03-01 | mem-cache: alias to mem::getMasterPort in TLB class | Andrea Mondelli |
| 2019-02-20 | x86: Call the base class's regStats in X86ISA::TLB | Bagus Hanindhito |
| 2019-02-12 | python: Replace dict.has_key with 'key in dict' | Andreas Sandberg |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | x86: Stop using/defining some ISA specific register types. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-24 | base: arch: Get rid of the now unused FloatRegVal type. | Gabe Black |
| 2019-01-22 | sim-se add readv and modifies writev | Brandon Potter |
| 2019-01-22 | sim-se: add ability to get/set sock metadata | Brandon Potter |
| 2019-01-22 | sim-se: add syscalls related to polling | Brandon Potter |
| 2019-01-22 | sim-se: add calls for network transmissions | Brandon Potter |
| 2019-01-22 | sim-se: add socket-based functionality | Brandon Potter |
| 2019-01-16 | arch: Make the ISA register types aliases for the global types. | Gabe Black |
| 2019-01-10 | sim-se: Refactor clone to avoid most ifdefs | Andreas Sandberg |
| 2018-12-05 | arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.cc | Tony Gutierrez |
| 2018-11-27 | sim-se: only implement getdentsFunc on supported hosts | Ciro Santilli |
| 2018-11-21 | x86: Get rid of a problematic DPRINTF in PremFp. | Gabe Black |
| 2018-10-17 | arch: Get rid of the unused type AnyReg. | Gabe Black |
| 2018-10-12 | x86: Use little endian packet accessors. | Gabe Black |
| 2018-09-19 | syscall_emul: implement dir-related syscalls | Brandon Potter |
| 2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
| 2018-08-21 | misc: Appease GCC 8 | Jason Lowe-Power |
| 2018-06-25 | syscall_emul: adding symlink system call | Matt Sinclair |
| 2018-06-25 | syscall_emul: adding link system call | Matt Sinclair |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-05-24 | x86: Add op classes to the MediaOps. | Gabe Black |
| 2018-05-08 | arch-x86, arch-power: fix calls to bits and insertBits | Matt Sinclair |
| 2018-05-03 | arch-x86: Enable fstatfs for x86_64 | Tony Gutierrez |
| 2018-05-02 | arch-x86: implement movntps/movntpd SSE insts | Steve Reinhardt |
| 2018-05-02 | x86: Add a ld/st microop flag for marking an access uncacheable. | Gabe Black |
| 2018-05-02 | arch-x86: Enable the umask system call | Tony Gutierrez |
| 2018-04-27 | sim,cpu,mem,arch: Introduced MasterInfo data structure | Giacomo Travaglini |
