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path: root/src/arch/x86
AgeCommit message (Expand)Author
2019-09-05arch-x86: Adding warning for movntiPouya Fotouhi
2019-09-05arch-x86: implement movntq/movntdq instructionsPouya Fotouhi
2019-08-16x86: Stop CPUID from claiming we support xsave.Gabe Black
2019-08-15x86: Make unsuccessful CPUID instructions zero the result.Gabe Black
2019-08-10x86: Move some fixed or dummy config information into X86LocalApic.py.Gabe Black
2019-08-06sim-se: add new getpgrp system callBrandon Potter
2019-08-06sim-se: adding pipe2 syscallMatthew Sinclair
2019-07-22arch-x86: Don't free PTW state with inflight requestsMatthew Poremba
2019-07-16arch-x86: add unconditional tag to calls/returnsHoa Nguyen
2019-05-31x86: fix movsd bug on %xmm registerBrandon Potter
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-22sim-se: remove comment for code that movedBrandon Potter
2019-05-21sim-se: change syscall function signatureBrandon Potter
2019-05-20x86: Add an object file loader for linux.Gabe Black
2019-05-07x86: Mark translation as delayed in case of a hw page table walkGabor Dozsa
2019-05-03sim-se: add eventfd system callBrandon Potter
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
2019-04-30x86: Get rid of some unnecessary TheISA-es in x86.Gabe Black
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-25x86: Refactor the ProcessInfo constructor.Gabe Black
2019-04-25x86: Fix some style issues in stacktrace.cc.Gabe Black
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
2019-02-20x86: Call the base class's regStats in X86ISA::TLBBagus Hanindhito
2019-02-12python: Replace dict.has_key with 'key in dict'Andreas Sandberg
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31x86: Stop using/defining some ISA specific register types.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-24base: arch: Get rid of the now unused FloatRegVal type.Gabe Black
2019-01-22sim-se add readv and modifies writevBrandon Potter
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
2019-01-22sim-se: add socket-based functionalityBrandon Potter
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
2018-12-05arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.ccTony Gutierrez
2018-11-27sim-se: only implement getdentsFunc on supported hostsCiro Santilli
2018-11-21x86: Get rid of a problematic DPRINTF in PremFp.Gabe Black
2018-10-17arch: Get rid of the unused type AnyReg.Gabe Black
2018-10-12x86: Use little endian packet accessors.Gabe Black