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AgeCommit message (Expand)Author
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
2019-12-10x86: Stop manually clearing RFLAGS.RF after a system call.Gabe Black
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
2019-12-10arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.Gabe Black
2019-12-05arch-x86: missing override specifierAndrea Mondelli
2019-12-05arch-x86: Adding LDDQU instructionmarjanfariborz
2019-11-26arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.Gabe Black
2019-11-20base,tests: Expanded GTests for addr_range.hhBrandon Potter
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
2019-11-07x86: Replace htog and gtoh with htole and letoh.Gabe Black
2019-11-02arch,cpu: Move endianness conversion of inst bytes into the ISA.Gabe Black
2019-11-01arch-x86: Fix FLDCW_P and FNSTCW_P to use rip.seanzw
2019-10-30arch,sim: Make copyStringArray take an explicit endianness.Gabe Black
2019-10-30arch: Make endianness a property of the OS class syscalls can consume.Gabe Black
2019-10-19arch: Make a base class for Interrupts.Gabe Black
2019-10-18x86: Turn the local APIC Interrupts class into a SimObject.Gabe Black
2019-10-16arch,base,sim: Move Process loader hooks into the Process class.Gabe Black
2019-10-15x86: Use a std::function to handle MSI completion.Gabe Black
2019-10-15arch-x86: Make LFENCE a serializing instructionIsaac Richter
2019-10-15x86: De-x86ify the IntMasterPort.Gabe Black
2019-10-14x86: Simplify and consolidate the code that assembles an MSI on x86.Gabe Black
2019-10-12x86: Stop using and delete the x86 IntDevice class.Gabe Black
2019-10-12arch,base: Separate the idea of a memory image and object file.Gabe Black
2019-10-10arch,base: Stop loading the interpreter in ElfObject.Gabe Black
2019-10-10arch, base: Stop assuming object files have three segments.Gabe Black
2019-10-09base: Rename Section to Segment, and some of its members.Gabe Black
2019-10-02x86: Switch from MessageReq and Resp to WriteReq and Resp.Gabe Black
2019-09-21x86: Templatize the IntMasterPort.Gabe Black
2019-09-21x86: Templatize IntSlavePort.Gabe Black
2019-09-21x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.Gabe Black
2019-09-20arch-x86: ignore non-temporal hint for movntps/movntpd SSE instsPouya Fotouhi
2019-09-19arch-x86: Change warn to warn_once for NT instructionsHoa Nguyen
2019-09-18arch, x86: Rework the debug faults and microops.Gabe Black
2019-09-05arch-x86: Adding warning for movntiPouya Fotouhi
2019-09-05arch-x86: implement movntq/movntdq instructionsPouya Fotouhi
2019-08-16x86: Stop CPUID from claiming we support xsave.Gabe Black
2019-08-15x86: Make unsuccessful CPUID instructions zero the result.Gabe Black
2019-08-10x86: Move some fixed or dummy config information into X86LocalApic.py.Gabe Black
2019-08-06sim-se: add new getpgrp system callBrandon Potter
2019-08-06sim-se: adding pipe2 syscallMatthew Sinclair
2019-07-22arch-x86: Don't free PTW state with inflight requestsMatthew Poremba
2019-07-16arch-x86: add unconditional tag to calls/returnsHoa Nguyen
2019-05-31x86: fix movsd bug on %xmm registerBrandon Potter
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-22sim-se: remove comment for code that movedBrandon Potter