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2019-10-02x86: Switch from MessageReq and Resp to WriteReq and Resp.Gabe Black
Originally MessageReq was intended to mark a packet as a holding a message destined for a particular recipient and which would not interact with other packets. This is similar to the way a WriteReq would behave if writing to a device register which needs to be updated atomically. Also, while the memory system *could* recognize a MessageReq and know that it didn't need to interact with other packets, that was never implemented. Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Templatize the IntMasterPort.Gabe Black
This makes the IntMasterPort usable with any class, making it possible to avoid inheriting from IntDevice. It also makes IntMasterPort inherit directly from QueuedMasterPort, skipping over MessageMasterPort. Change-Id: I9d218556c838ea567ced5f6fa4d57a3ec9d28d31 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20821 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Templatize IntSlavePort.Gabe Black
This makes the device IntSlavePort calls back into based on a template parameter so that IntDevice doesn't have to be in the inheritance hierarchy to use it. It also makes IntSlavePort inherit from SimpleTimingPort directly, skipping over MessageSlavePort. Change-Id: Ic3213edc9c3ed5e506ee1e9f5e082cd47d7c7998 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20820 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.Gabe Black
This will let us accept several address ranges through our pio port instead of just one, and that will in turn let us accept interrupt requests and pio requests through the same port. Change-Id: I70b78c8cd0edca7fe58b3d4cd241e41d9e0f2c20 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20819 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-20arch-x86: ignore non-temporal hint for movntps/movntpd SSE instsPouya Fotouhi
Making the implementation of movntps/movntpd consistent with other non-temporal instructions. We are ignoring the hint here, and implementing those instructions as cacheable instructions. This change adds a warning to let user know about this workaround. Also, this change add the address check for second part of move. Change-Id: I811652b24cf39ca2f5c5d4c9e9e417f69190b55c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20408 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19arch-x86: Change warn to warn_once for NT instructionsHoa Nguyen
Change-Id: I50353716f2a913b9b106b140644d95991879f662 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch, x86: Rework the debug faults and microops.Gabe Black
This makes the non-fatal microops advance the PC, and adds missing functions. The *_once Faults now also can be run once per *something*. They would previously be run once per Fault invoke function which is common to all M5WarnOnceFaults. The warn_once microop will now warn once per message. Change-Id: I05974b93f3b2700077a411b243679c2ff0e8c2cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20739 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05arch-x86: Adding warning for movntiPouya Fotouhi
We are ignoring the non-temporal hint here, and implementing this instruction as a cacheable instruction. This change adds a warning to let user know about this workaround. Change-Id: I2e40437a44282fe9cf7772a25a8870bd8729a6ed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20428 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-05arch-x86: implement movntq/movntdq instructionsPouya Fotouhi
Non-temporal quadword/double-quadword move instructions. This change ignores the non-temporal hint and instructions are implemented to send cacheable request to memory. This would have some "performance" impact (i.e. having some cache pollution) to get better "correctness" in behavior. Change-Id: I2052ac0970f61a54bafb7332762debcb7103202d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20288 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-16x86: Stop CPUID from claiming we support xsave.Gabe Black
xsave is a fairly complex feature which we don't support in gem5, but we do report that we support it through CPUID. It looks like I confused it with FXSAVE which is an instruction related to SSE. This change turns that bit back off again. Change-Id: I00fc79168c5f7095b5241e870a4c8782e4385425 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20169 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-15x86: Make unsuccessful CPUID instructions zero the result.Gabe Black
The previous implementation left the registers unmodified which is technically correct since there is no defined behavior in that case or a fault to raise. That would make what happened when the following code consumed the result unpredictable because it would depend on what junk values were left in the registers. This was originally not a problem since the space of supported functions were tightly packed, but someone added a new function with a gap without adjusting this behavior. This change makes CPUID zero out RAX, RBX, RCX, and RDX when it fails. That should be more predictable and cause less flakey failures. Change-Id: If6ffb17c2969d34aff1600c0ffc32333d0b9be44 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20168 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-10x86: Move some fixed or dummy config information into X86LocalApic.py.Gabe Black
The X86 local APIC doesn't actually use the pio_addr set in the config and instead computes what address it will respond to based on the initial ID of the CPU it's attached to. gem5's BasicPioDevice, which the X86LocalApic class inherits from, does not provide a default value for that parameter and will complain if *something* isn't set. The value used, 0x2000000000000000, is a dummy value which is the base of the region of the physical address space set aside for messages to local APICs from the CPU and from other local APICs. Also, the clock for the local APIC's timer is defined to be the bus clock. The assumption seems to be that this has a 16:1 ratio with the CPU clock, and I vaguely remember finding that that was more or less unofficially true, even if it isn't necessary stringently defined to be that. Since we were already just assuming that that ratio was correct and always setting up the local APICs clock that way, we can do that in the X86LocalApic class definition and remove some special x86 specific setup that we'd otherwise need for the x86 version of the Interrupt class. If that's not correct, it can still be overridden somewhere else in the config. Change-Id: I50e84f899f44b1191c2ad79d05803b44f07001f9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19968 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-06sim-se: add new getpgrp system callBrandon Potter
This changeset adds new (relatively simple) system call support. The getpgrp call returns a thread context's pgid. Change-Id: I361bdbfb9c01b761ddd5a4923d23f86971f8d614 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17111 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
2019-08-06sim-se: adding pipe2 syscallMatthew Sinclair
pipe2 builds on top of the pipe syscall implementation by adding some extra flags for the files (to avoid have to make separate calls to fcntl). Change-Id: I88cf6f1387b9d14e60b33a32db412da9ed93a3e6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12310 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-22arch-x86: Don't free PTW state with inflight requestsMatthew Poremba
If a page table walk is squashed, the walker state is being deleted in the squash code. If there are in flight requests, the deleted walker state values may be clobbered, leading to undefined behavior. This adds a squashed boolean to the walker state which is set if a walk is squashed while requests are still in flight. When packets for the in flight request return, we check if the walk was squashed and return that the walk is complete once the number of in flight requests reaches zero. The walker state is then freed by the PTW. Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19568 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-16arch-x86: add unconditional tag to calls/returnsHoa Nguyen
The branch predictor checks whether an instruction is unconditional branch before adding it or checking the RAS. With this change, the RAS is significantly more effective for short running x86 workloads. Change-Id: I60af5f2f583b898ad77f79f4b0478d6cda88fc21 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19448 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2019-05-31x86: fix movsd bug on %xmm registerBrandon Potter
The movsd instruction should zero out half the register, but does not do it. This changeset adds the necessary microop to the instruction to cause correct behavior. Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
These two functions were performing the same function but had two different names for historical reasons. This change merges them together, keeping the getVirtProxy name to be consistent with the getPhysProxy method used to get a non-translating proxy port. Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
Al(most) all of the interesting differences between the two classes have been removed. There are some control methods which are still specific to each type which may require treating them as their true type, but most code that consumes them doesn't need to worry about which is which. Change-Id: Ie592676f1e496c7940605b66e55cd7fae18e59d6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18577 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
This expands those functions into code which extracts the virt proxy and then uses the appropriate method on it. This has two benefits. First, the Copy* functions where mostly redundant wrappers around the methods the proxy port already had. Second, using them forced a particular port which might not actually be what the user wanted. Change-Id: I62084631dd080061e3c74997125164f40da2d77c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18575 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
Set the default release to that single value for all ISAs. glibc has checks for the kernel version based on uname, and refuses to start any syscall emulation programs if those checks don't pass with error: FATAL: kernel too old The ideal solution to this problem is to actually implement all missing system calls for the required kernel version and bumping the release accordingly. However, it is very hard to implement all missing syscalls and verify compliance. Previously, we have simply bumped the version manually from time to time when major glibc versions started breaking. This commit alleviates the problem in two ways. Firstly, having a single kernel version for all versions means that it is easier to bump all versions at once. Secondly, it makes it is possible to set the release with a parameter, which in turn can be set from the command line with: se.py --param 'system.cpu[:].workload[:].release = "4.18.0"' Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-22sim-se: remove comment for code that movedBrandon Potter
The page table code must have moved from this class, because the comment no longer accurately reflects upon any of the surrounding code. Change-Id: If08a4298c1237a541d9875ddeaf3d3ecfd98e9db Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12300 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-05-21sim-se: change syscall function signatureBrandon Potter
The system calls had four parameters. One of the parameters is ThreadContext and another is Process. The ThreadContext holds the value of the current process so the Process parameter is redundant since the system call functions already have indirect access. With the old API, it is possible to call into the functions with the wrong supplied Process which could end up being a confusing error. This patch removes the redundancy by forcing access through the ThreadContext field within each system call. Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20x86: Add an object file loader for linux.Gabe Black
Change-Id: I283dd1f52fd020ad3c226eb00fc9216ee034c67f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18630 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-07x86: Mark translation as delayed in case of a hw page table walkGabor Dozsa
This information is used by the LSQ in the O3 cpu (since commit "51becd2... cpu-o3: O3 LSQ Generalisation") Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-03sim-se: add eventfd system callBrandon Potter
Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12125 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
We know for sure what the ISA is, so there's no need for the indirection. Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30x86: Get rid of some unnecessary TheISA-es in x86.Gabe Black
The X86ISA namespace is already available. Change-Id: I5774968fdfb30b01eba52cdec5e6ef2c75cb66e4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18471 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
The AuxVector type has a bunch of accessors which just give access to the underlying variables through references. We might as well just make those members accessible directly. Also, the AuxVector doesn't need to handle endianness flips itself. We can tell the byteswap mechanism how to flip an AuxVector, and let it handle that for us. This gets rid of the entire .cc file which was complicated by trying to both hide the ISA specific endianness translations, and instantiate templated functions in a .cc. Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
These selected their behavior based on ifdefs and had to be disabled when on the NULL ISA. The versions which take an explicit endianness have been renamed to just read/write instead of readGtoH and writeHtoG since the direction of the translation is obvious from context. Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28mem: Minimize the use of MemObject.Gabe Black
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-25x86: Refactor the ProcessInfo constructor.Gabe Black
That function had a lot of repetition which is easily factored out into its own function. Change-Id: I3b7a522de2ba808856bb59df75b80efde6780e3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18369 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-25x86: Fix some style issues in stacktrace.cc.Gabe Black
De-indent the X86ISA namespace, and wrap some overly long lines. Change-Id: I01a6b66a1cf721e16e4ed4dd1c3469ee112e9177 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18368 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
This changeset enables clone to work with X86KvmCPU model, which will allow running multi-threaded applications at near hardware speeds. Even though the application is multi-threaded, the KvmCPU model uses one event queue, therefore, only one hardware thread will be used, through KVM, to simulate multiple application threads. Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-20x86: Call the base class's regStats in X86ISA::TLBBagus Hanindhito
When I try to build x86 architecture and run the se.py sample script with helloworld example, there is a panic warning stated "Not all stats have been initialized. You may need to add <ParentClass>::regStats() to a new SimObject's regStats() function." I see that in x86 tlb.cc, there is no initialization in regStats() function that causes memory allocation error in some machine which make gem5 exit abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and can solve the problem Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f Reviewed-on: https://gem5-review.googlesource.com/c/16522 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-12python: Replace dict.has_key with 'key in dict'Andreas Sandberg
Python 3 has removed dict.has_key in favour of 'key in dict'. Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15987 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
Most architectures weren't using the CCReg type, and in x86 and arm it was already a uint64_t. Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6 Reviewed-on: https://gem5-review.googlesource.com/c/14515 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31x86: Stop using/defining some ISA specific register types.Gabe Black
These have been replaced with the generic RegVal type. Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6 Reviewed-on: https://gem5-review.googlesource.com/c/14476 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-24base: arch: Get rid of the now unused FloatRegVal type.Gabe Black
This type is no longer used since FP registers are accessed as integer bit patterns. Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f Reviewed-on: https://gem5-review.googlesource.com/c/14459 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-22sim-se add readv and modifies writevBrandon Potter
Change-Id: I6cbce4389d5697da34058dc910306394e48c6582 Reviewed-on: https://gem5-review.googlesource.com/c/12117 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
Add getsockopt, getsockname, setsockname, and getpeername system calls. Change-Id: Ifa1d9a95f15b4fb12859dbfd3c4bd248de2e3d32 Reviewed-on: https://gem5-review.googlesource.com/c/12116 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
Fix poll so that it will use the syscall retry capability instead of causing a blocking call. Add the accept and wait4 system calls. Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls. Modify the write system call to return an error number in case of error. Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
Add recvfrom, sendto, recvmsg, and sendmsg system calls. Change-Id: I2eb50ea7823c8af57d99b3b8d443d2099418c06c Reviewed-on: https://gem5-review.googlesource.com/c/12114 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add socket-based functionalityBrandon Potter
Add socket, socketpair, bind, list, connect and shutdown system calls. Change-Id: I635af3fca410f96fe28f8fe497e3d457a9dbc470 Reviewed-on: https://gem5-review.googlesource.com/c/12113 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 17:26:44 +0000