gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-31	power: Get rid of some ISA specific register types.	Gabe Black
2019-01-31	null: Get rid of some register type definitions.	Gabe Black
2019-01-31	mips: Stop using architecture specific register types.	Gabe Black
2019-01-31	alpha: Stop using architecture specific register types.	Gabe Black
2019-01-31	x86: Stop using/defining some ISA specific register types.	Gabe Black
2019-01-31	riscv: Get rid of some ISA specific register types.	Gabe Black
2019-01-31	arch: cpu: Rename FloatRegBits to FloatReg.	Gabe Black
2019-01-30	arch,cpu: Add vector predicate registers	Giacomo Gabrielli
2019-01-30	arch-arm, configs: Create single instance of DTB autogeneration	Giacomo Travaglini
2019-01-25	arch-arm: Remove floatReg operand type	Giacomo Travaglini
2019-01-25	arch-arm: Use VecElem instead of FloatReg for FP instruction	Giacomo Travaglini
2019-01-25	arch: Fix VecElem Operand generation in ISA parser	Giacomo Travaglini
2019-01-25	cpu, arch, arch-arm: Wire unused VecElem code in the O3 model	Giacomo Travaglini
2019-01-25	arch-arm: Inital vector rename mode depending on A32/A64	Giacomo Travaglini
2019-01-25	arch-arm: Remove unused float operands	Giacomo Travaglini
2019-01-25	arch: Provide traceback when parsing ISA code	Giacomo Travaglini
2019-01-24	hsail: Remove the MiscReg type.	Gabe Black
2019-01-24	base: arch: Get rid of the now unused FloatRegVal type.	Gabe Black
2019-01-23	arch-arm: Implement LoadAcquire/StoreRelease in AArch32	Giacomo Travaglini
2019-01-23	arch-arm: IsStoreConditional flag set depending on flavor	Giacomo Travaglini
2019-01-23	arch-arm: Remove SWP and SWPB instructions	Giacomo Travaglini
2019-01-23	arm: Replace MiscReg with RegVal in utility.(hh\|cc).	Gabe Black
2019-01-22	sparc: Get rid of some register type definitions.	Gabe Black
2019-01-22	arch: cpu: Stop passing around misc registers by reference.	Gabe Black
2019-01-22	arm: Get rid of some register type definitions.	Gabe Black
2019-01-22	arch-arm: implement the GDB XML target description for ARM	Ciro Santilli
2019-01-22	arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers	Giacomo Travaglini
2019-01-22	sim-se add readv and modifies writev	Brandon Potter
2019-01-22	sim-se: add ability to get/set sock metadata	Brandon Potter
2019-01-22	sim-se: add syscalls related to polling	Brandon Potter
2019-01-22	sim-se: add calls for network transmissions	Brandon Potter
2019-01-22	sim-se: add socket-based functionality	Brandon Potter
2019-01-16	cpu: dev: sim: gpu-compute: Banish some ISA specific register types.	Gabe Black
2019-01-16	arch: Make the ISA register types aliases for the global types.	Gabe Black
2019-01-16	arm: Make the fp register types 64 bits.	Gabe Black
2019-01-16	arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled	Giacomo Travaglini
2019-01-16	arch-arm: Added TLBI_ALL EL2 instruction	Anouk Van Laer
2019-01-16	arch-riscv: Add interrupt handling	Alec Roelke
2019-01-16	arch-riscv: Fix reset function and style	Alec Roelke
2019-01-15	arch-arm: Fix usage of RegId constructor for VecElem	Giacomo Travaglini
2019-01-14	arm: Stop using the FloatReg and FloatRegBits types.	Gabe Black
2019-01-10	sim-se, arch-arm: Add support for getdents64	Javier Setoain
2019-01-10	arch-arm, sim-se: Add support for TLS in clone	Andreas Sandberg
2019-01-10	arch-arm, sim-se: Fix incorrect SP handling in clone	Andreas Sandberg
2019-01-10	sim-se: Refactor clone to avoid most ifdefs	Andreas Sandberg
2019-01-10	arch-arm, sim-se: Wire up syscalls needed for pthreads	Javier Setoain
2019-01-10	dev-arm: Add a GICv3 model	Jairo Balart
2019-01-09	arch-arm: Additional bits in misc ARM registers to use with the TLB and page ...	Ivan Pizarro
2019-01-03	arm: properly handle RES0/1 for SCTLRs	Curtis Dunham
2018-12-20	arch, cpu: Remove float type accessors.	Gabe Black