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2019-12-01arch-riscv: Fix disassembling of immediate for c.lui instructionIan Jiang
For compressed instruction c.lui, the 6-bit immediate is left-shifted by 12 bits in decoding. While the original Gem5 gives the left-shifted value directly in disassembly. This patch fixes the problem by adding a new template CILuiExecute to resume the immediate before outputting it in disassembly. Note: The immediate is sign-extended to 20-bit to be compatible with GCC. Change-Id: If73f72d3e8f85a8b10ce7a323379d8ad6c4c3085 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22567 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28arm: Make sure not to shift off of the end of a uint32_t in KVM.Gabe Black
The methods which set or get an attribute from the virtual GIC use a shift constant which is 32, but they store their result in a 32 bit variable and, according to clang, are used to shift 32 bit inputs. This is undefined behavior in terms of the shift, and will truncate off the value regardless. Change-Id: Ie9543ab9e6e1d5f86317a9210d220928b23ffaf8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23129 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-26arch-arm: Make the Tarmac parsed registers case insensitiveGiacomo Travaglini
This will make parsing more robust, considering the tarmac format changes between AA32 and AA64. Change-Id: I0e4905d70e2e494104706a4c6c75b8169deaecf9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22845 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch-riscv: Fix immediate decoding for integer shift immediate instructionsIan Jiang
The "shamt" in integer shift immediate instructions is an unsigned immediate encoded in bits[25:20]. While the original Gem5 uses bits[31:20] as an int64_t. This patch fixes the problem by: - Adding a new parameter "imm_code" for format IOp and use the correct bitfields SHAMT5 or SHAMT6 to assign "imm_code" for each instruction. - Use uint64_t instead of default int64_t to assign parameter "imm_type" of format IOp. The instructions affected include: - Shift Left Logical Immediate, slli - Shift Right Logical Immediate, srli - Shift Right Arithmetic Immediate, srai - Shift Left Logical Word Immediate, slliw - Shift Right Logical Word Immediate, srliw - Shift Right Arithmetic Word Immediate, sraiw Change-Id: Iad34ccd036c11630409f84f6de2b939224e100e6 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22563 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch-riscv: Fix disassembling for fence and fence.iIan Jiang
The original Gem5 does not give correct disassembly for instruction fence and fence.i. This patch fixes the problem by adding two bitfields PRED and SUCC and a new format FenceOp and a template FenceExecute, in which operands are generated based on PRED and SUCC in the disassembling function. Change-Id: I78dbf125fef86ce40785c498a318ffb1569da46c Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22569 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-26arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.Gabe Black
This conditional compilation was unnecessary and makes gem5 more brittle and harder to understand. Change-Id: I63abaf2668252c988cdd4626ff6a462eb6f54b04 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22544 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25arm: Stop serializing ISA values wihch are cached from the system.Gabe Black
These values are not really part of the ISA state and could be retrieved from the system during execution. Also these values are already being set in the ISA constructor. Change-Id: Iea5f9bbb27add4ecebc6391da6c1c1e49e76508f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22543 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25arch-arm: default MIDR for Armv8 ISA processorsAdrian Herrera
Software such as Trusted Firmware-A checks the MIDR register to identify which core model is present in the platform. The previous default value referred to a Cortex-A15 Armv7-A processor, however when AArch64 is enabled, an Armv8 processor is expected. This patch assigns the Cortex-A57 MIDR if AArch64 is enabled. Change-Id: Id1677a77d2f04843423f7b013405445f3d253399 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22846 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25arch-riscv: Fix disassembling for atomic instructionsIan Jiang
The original Gem5 does not give correct disassembly for atomic instructions, which are implemented with one or two micro instructions. The correct register indices are not decoded until subsequent micro instruction is processed. This patch fixes the problem by getting the register indices and other properties (aq and rl) from certain bitfields of the machine code in the disassembling function. Change-Id: I2cdaf0b3c48ff266f19ca707a5de48c9050b3897 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22568 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-25arch-riscv: Fix disassembling of operand list for compressed instructionsIan Jiang
In disassembling compressed instructions, the original Gem5 gives needless operands, such as register or immediate. This patch fixes the problem. - Existing formats fixed: CIOp, CJOp, CBOp and Jump. - New formats added: CIAddi4spnOp (for c.addi4spn only) and CompressedROp (with templates CBasicDeclare and CBasicExecute) Change-Id: Ic293836983256a59d3a7aca091c8184b410516a4 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22566 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-11-25arch-riscv: Fix disassembling of immediate for U-type instructionsIan Jiang
For U-type instructions auipc and lui, the 20-bit immediate is left-shifted by 12 bits in decoding. While the original Gem5 gives the left-shifted value directly in disassembly. This patch fixes the problem by - Assign the original 20-bit immediate to internal variable "imm". - Output "imm" directly in disassembly, as how the original Gem5 does. - Do the left-shift to "imm" later in the function defining of each instruction, rather than in decoding. Change-Id: I300e26fd9c79478783c39fcd6ff70ea06db88884 Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22564 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-22arch-riscv: Fix bug in serialize and unserialize of InterrutpsIanJiangICT
When serialize and unserialize an variable, the parameters passed to SERIALIZE_SCALAR() and UNSERIALIZE_SCALAR() must be the same and should be a general variable name. If not, the expected item would not be found with UNSERIALIZE_SCALAR() and a fatal error would be introduced. This patch fix the bug in class Interrupts of RISCV. Change-Id: I7dd7ab6805651149304959bdf7ee9f3be9d9eaff Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22643 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-11-20base,tests: Expanded GTests for addr_range.hhBrandon Potter
These tests assume the "end address" is not included in the range. This exposed some bugs in addr_range.hh which have been fixed. Where appropriate code comments in addr_range.hh have been extended to improve understanding of the class's behavior. Hard-coded AddrRange values in the project have been updated to take into account that end address is now exclusive. The python params.py interface has been updated to conform to this new standard. Change-Id: Idd1e75d5771d198c4b8142b28de0f3a6e9007a52 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22427 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
These namespaces were used to set up an environment/context where there was an implicit guest namespace. This is an issue when there may be multiple guest endiannesses which might be different. In cases where we don't know what the guest endianness is, we can't rely on it being an implicit part of our context since that would be ambiguous. In cases where we do know, for instance in ISA specific code, we can just use the endianness specific version that's appropriate for that context. This also (somewhat) removes the assumption that there is a single endianness that applies for a particular ISA. Practically speaking this assumption will probably still stand though, since there would likely be a non-trivial performance penalty to apply a configurable endianness instead of a fixed one the compiler can optomize/remove. Change-Id: I2dff338b58726d724f387388efe32d9233885680 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22374 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
Rather than using TheISA to pick an endian conversion function, we can have a version defined for big and little endian and call the right one from the ISA code. Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: R/W interface to AArch32 HCR2 misc regAdrian Herrera
This patch implements read/write interfaces to HCR2 AArch32 register, which is mapped to the upper 32 bits of HCR_EL2. Change-Id: I996023f3ad8233457d19de8a506ebcf106409165 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: Fix short descriptors cacheability during table walksGiacomo Travaglini
This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits. Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724 Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: Fix long descriptors cacheability during table walksGiacomo Travaglini
Prior to this patch table walks were always cacheable unless cacheability was globally disabled by SCTLR.C being 0. Arm allows to select the memory attributes of table walks via the TCR registers. For example the TCR.IRGN0 bits: Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. IRGN0 Meaning 0b00 Normal memory, Inner Non-cacheable. 0b01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. 0b10 Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. 0b11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. Note: we check IRGNx bits (Inner Shareable domain) instead of ORGNx (Outer Shareable domain) since in gem5 we consider everything as Inner Shareable. Change-Id: If472c218040029c9d165b056a052f522d48d4a82 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22723 Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14arch-arm: Refactor code to check if gic is GicV2Chun-Chen TK Hsu
Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is only meanful to GicV2. Test: Boot Android P successfully with the following command: M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel $PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img --kernel-init "/init" --cpu-type fastmodel --machine-type VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0 --mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2 android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5 androidboot.selinux=permissive audit=0 cma=128M" Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-14config: Add fastmodel cluster in fs_bigLITTLE.pyChun-Chen TK Hsu
One can create a system with ARM FastModels CPU and GICv3 with --cpu-type fastmodel --machine-type VExpressFastmodel options. Currently the FastmodelCluster only supports one CPU. Change-Id: I2e985f08f9df01a703e21441c6f9bc1fbae4a222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20901 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-13arm: Replace most htog and gtoh with htole and letoh.Gabe Black
We already know what endianness to use when with ARM. In places where a ISA was being supplied through an argument, those were left as htog or gtoh. Change-Id: Iff01e8b09a061d9a72e657cdd4570836e0da933f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22372 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-13arch-arm: fix routeToHyp for AArch64 in faultsAdrian Herrera
This patch fixes several bugs in Fault classes "routeToHyp" member function by which mode checking was not taking into account AArch64 execution state. For the particular case of SVC calls from NS EL0, this prevented a correct routing to EL2 when HCR_EL2.TGE was set. Change-Id: I5815fe6dcf4501f52bf92f61687ef6d6ef950e52 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22725 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
2019-11-13fastmodel: Implement reading vector registers with readVecReg.Gabe Black
The n other flavors of vector reading functions and all the vector writing functions are not implemented currently. Change-Id: I0c25c3ba47c7e4072da3d28596f44f6073b6f609 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22117 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-11arch-arm: Fix TarmacParser handling of 64bit LD/STGiacomo Travaglini
The TarmacParser was assuming 32 bit accesses only. This was creating a mismatch when parsing a trace with 64 bit accesses. E.g. In clk IT (18) 002001f4 f8008441 O EL3h_s : STR x1,[x2],#8 clk MW8 00201008:000000201008 00000000_40000401 Only the 32 MSBs were checked (00000000) Change-Id: I51e803b53efe953edcd9378f6c9481c04932331e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21562 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-11arch-arm: Provide SVE support to the TarmacTracerGiacomo Travaglini
Change-Id: I86ff5f49a0c0aa126d53076964f208716e70aacb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21561 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-11arch-arm: Provide SVE support to the TarmacParserGiacomo Gabrielli
This patch is providing SVE support to the tarmac parser, so that it is recognizing Vector & Predicate entries. Change-Id: I268e621cffa05644d3f1d80170b067aacaa2d5ea Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21560 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07arm: Set the number of FloatRegs to zero.Gabe Black
ARM no longer uses the floating point register file and uses the vector registers instead. This avoids checkpointing a bunch of unused registers, making it hard to tell where floating point instructions are keeping their values, etc. Change-Id: I23145ba750f1dd9ff5b815395e073c410120840d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22524 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07power: Replace gtoh and htog with betoh and htobe.Gabe Black
We already know what endianness to use when within power. Change-Id: Id4ced279d21c56855307a5a8da51654101a13786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22371 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07x86: Replace htog and gtoh with htole and letoh.Gabe Black
We already know what endianness to use from within x86. Change-Id: Ie92568efe8b23fbb7d9edad55fef09c6302cbe62 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22370 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07mips: Replace gtoh and htog with letoh and htole.Gabe Black
We already know what endianness to use from within MIPS. Change-Id: Ic4cd295a7a66c4c8ef55ebcf976fe6637567391f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22369 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07sparc: Replace htog and gtoh with htobe and betoh.Gabe Black
We know what endianness to use when we're implicitly working with SPARC. Change-Id: I85eaac1da087a8086b9450b762a52323f2498e2e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22368 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07fastmodel: Plumb the ITB and DTB through the IRIS thread context.Gabe Black
These might be necessary to, for instance, translate virtual addresses. A custom TLB which uses the IRIS API will be written which can be substituted in for the normal ARM TLB. Change-Id: Ic44822db6692ca3a4ca13875b2260b08547a24da Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22116 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-06fastmodel: Implement inst count events in the IRIS thread contexts.Gabe Black
These use the IRIS stepping API. Change-Id: Ib45744cb0928fece664187e4df6b25b064b19f0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22115 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-06arch-arm: Simplify AMO code generation templatesNikos Nikoleris
This change simplifies the isa template for the atomic memory operation (AMO). Previously the flow had unecessary if statements that ended up breaking build using clang, due to variables that could seemingly be used before they were unitialized. Change-Id: I1b46dfd5f1e90377245c4f649c08b6532b507b9c Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22603 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05arch-arm: Annotate original address in CMOsGiacomo Travaglini
This is needed when a CMO triggers an exception (e.g. DataAbort) In that case the faulting address should be the one encoded in the instruction rather than the cacheline address: According to armarm: If a memory fault that sets FAR_EL1 is generated from a data cache maintenance or other DC instruction, FAR_EL1[63:0] holds the address specified in the register argument of the instruction. Change-Id: I6d0dadbef6e70db57438b01a76c5def3bdd2d974 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22443 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-02arch,cpu: Move endianness conversion of inst bytes into the ISA.Gabe Black
It doesn't matter if the bytes are converted before or after they're fed into the decoder. The ISA already knows what endianness to use implicitly, and this frees the CPU which doesn't from having to worry about it. Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01arch-x86: Fix FLDCW_P and FNSTCW_P to use rip.seanzw
FLDCW_P and FNSTCW_P should use rip to compute address. Change-Id: Ide7327e243d42bdd8791e43773385b2a79d45418 Signed-off-by: Zhengrong Wang <seanzw@ucla.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22483 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01arch-arm: generic method for getting an ArmSystemAdrian Herrera
This patch provides a generic method for casting a System object into an ArmSystem object. This is specially useful in dev-arm, since devices by default obtain a generic System reference which needs to be casted to use ArmSystem-specific functionality. Change-Id: Ib100002413cb48cd93772dcf38f13be65badd1d3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22426 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Add CortexA76x[234] models.Gabe Black
These use the parameterization added in earlier commits. Change-Id: Id7b99b97894f8fc1f1e5cc34e3e5d32146fed1c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21505 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Enable auto bridging and use it to simplify CortexA76x1.Gabe Black
This lets us avoid having to set up bridges for all the different interrupt signals coming out of the CPU. When we have more cores, like in the x2, x3, and x4 versions of the CPU, we won't have to have a set of bridges for each set of signals, and can connect them all to external ports using array notation, keeping everything simple, concise, and maintainable. Change-Id: I1a5f707073868516e93c106dc17d105409de668a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21504 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Templatize the xn versions of the CortexA76.Gabe Black
This will make it a lot easier and more succinct to define the x2-x4 versions of that CPU. Change-Id: I951cd3af4419c62892c57968e729fd11c0e4a59e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21503 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31alpha: Convert htog and gtoh to htole and letoh.Gabe Black
When within the Alpha arch, we know the guest endianness already. Change-Id: Iee22a33451a06c6e6a5c7d1e8c71f0b00e98ae3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22367 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-30arch,sim: Make copyStringArray take an explicit endianness.Gabe Black
Change-Id: I5cf4291b19dd2d2bdbbf145ad8e00994fabf5547 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22366 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30arch: Make endianness a property of the OS class syscalls can consume.Gabe Black
That way the syscall implementations won't have to find the right endianness to use on their own, typically by referring to TheISA. Change-Id: I186b2f419d5dbee72cc9b5abce7356f3143f0c83 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22363 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30fastmodel: Refactor the CortexA76x1 model for MP support.Gabe Black
This change inverts the relationship between the fast model and gem5 CPUs, and factors out the parts of the CortexA76x1 which are per core vs. per cluster. Change-Id: I33eacc2461f08c7fd1784936b230e96c768c0e79 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21501 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30fastmodel: Helper function to setup FastModels for simulationChun-Chen TK Hsu
This function sets up ARM license, simulation name, and minimum synchronize latency in FastModels. This function should be called once per simulation. Change-Id: Ic3408955aaff9f8b4e2b72d2f2b0da97b41bfc3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22183 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30sparc: Create a helper functions to install firmware images.Gabe Black
The first function handles the repetitive process of creating an ObjectFile for a particular purpose and checking if that was successful. The second conditionally offsets the images in case they were, for instance, loaded from an ELF file which already had them in the right place. It offsets them so that their entry point (which will be zero for raw images) lines up with the appropriate entry address (which will be at the start of raw images). This is more correct in more cases, and also removes a lot of redundancy. There's still a lot of redundancy in the code which sets up the symbol tables, but there are some irregularities which make that harder to wrap in a helper function. Change-Id: I2fee8b2175faff284ff9e007307f7769043497a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21469 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25mips,riscv: Get rid of some Alpha cruft in these System classes.Gabe Black
The consolePanicEvent pointer and addConsoleFuncEvent template were inherited from Alpha and were not used (and probably make no sense) for MIPS or RISCV which (to my knowledge) don't have the idea of a "console" binary. Change-Id: I109b866a65f69c7334062f7304c7b18acc51d99d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21782 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-25cpu: Get rid of the nextInstEventCount method.Gabe Black
This was only used by the KVM CPU, and it has access to all it needs to figure out that value locally without requiring all the ThreadContexts to implement an equivalent function. Change-Id: I17a14ce669db2519edf129db761ebd8dc3bd4129 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22114 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Get rid of the serviceInstCountEvents method.Gabe Black
This was useful when transitioning away from the CPU based comInstEventQueue, but now that objects backing the ThreadContexts have access to the underlying comInstEventQueue and can manipulate it directly, they don't need to do so through a generic interface. Getting rid of this function narrows and simplifies the interface. Change-Id: I202d466d266551675ef6792d38c658d8a8f1cb8b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22113 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-22 06:35:03 +0000