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2010-02-12O3PCU: Split loads and stores that cross cache line boundaries.Timothy M. Jones
When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.
2010-02-12Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.Timothy M. Jones
2009-11-05compile: compile on 32 bit hardwareNathan Binkert
2009-11-05isa_parser: allow negative integer literalsNathan Binkert
2010-01-19util: do checkpoint aggregation more cleanly, fix last changeset.Lisa Hsu
1) Move alpha-specific code out of page_table.cc:serialize(). 2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up. 3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN. 4) Fix the memory unserialize that I forgot somehow in the last changeset. 5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py. Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
2009-12-31MIPS: Beef up process initialization.Matt DeVuyst
2009-12-31MIPS: Implement the SE mode version of rdhwr.Gabe Black
2009-12-31MIPS: Fix decoding of the rdhwr instruction.Gabe Black
2009-12-31MIPS: Implement the set_thread_area system call.Gabe Black
2009-12-31MIPS: Create an artificial control register to hold the thread pointer.Gabe Black
In Linux, the set_thread_area system call stores the address of the thread local storage area into a field of the current thread_info structure. Later, to access that value, the program uses the rdhwr instruction to read a "hardware register" with index 29. The 64 bit MIPS manual, volume II, says that index 29 is reserved for a future ABI extension and should cause a "Reserved Instruction Exception". In Linux (and potentially other ISAs) that exception is trapped and emulated to return the value stored by set_thread_area as if that were actually stored by a physical register. The tp_value address (as named in the Linux kernel) is ironically stored as a control register so that it goes with a particular ThreadContext. Syscall emulation will use that to emulate storing to the OS's thread info structure, and rdhwr will emulate faulting and returning that value from software by returning the value itself, as if it was in hardware. In other words, we fake faking the register in SE mode. In an FS mode implementation it should work as specified in the manual.
2009-12-31MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.Gabe Black
The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.
2009-12-21MIPS: Add missing syscall slots.Gabe Black
These are all after the existing ones, suggesting they were added after the original list was created.
2009-12-20Alpha: Implement MVI and remaining BWX instructions.Soumyaroop Roy
2009-12-19X86: Add a common named flag for signed media operations.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate high multiplies.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate scalar media instructions.Gabe Black
2009-11-17ARM: Begin implementing CP15Ali Saidi
2009-11-17ARM: Differentiate between LDM exception return and LDM user regs.Ali Saidi
2009-11-17ARM: Boilerplate full-system code.Ali Saidi
--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-16imported patch isa_fixes2.diffAli Saidi
2009-11-15ARM: Make the exception return form of ldm restore CPSR.Gabe Black
2009-11-15ARM: Create a new type of load uop that restores spsr into cpsr.Gabe Black
2009-11-14ARM: Check in the actual change from the last commit.Gabe Black
The last commit was somehow empty. This was what was supposed to go in it.
2009-11-14ARM: Fix up the implmentation of the msr instruction.Gabe Black
2009-11-14ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.Gabe Black
2009-11-14ARM: Add a bitfield to indicate if an immediate should be used.Gabe Black
2009-11-14ARM: Write some functions to write to the CPSR and SPSR for instructions.Gabe Black
2009-11-14ARM: Fix up the implmentation of the mrs instruction.Gabe Black
2009-11-14ARM: More accurately describe the effects of using the control operands.Gabe Black
2009-11-14ARM: Hook up the moded versions of the SPSR.Gabe Black
These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode.
2009-11-14ARM: Move around decoder to properly decode CP15Ali Saidi
2009-11-11X86: add ULL to 1's being shifted in 64-bit valuesVince Weaver
Some of the micro-ops weren't casting 1 to ULL before shifting, which can cause problems. On the perl makerand input this caused some values to be negative that shouldn't have been. The casts are done as ULL(1) instead of 1ULL to match others in the m5 code base.
2009-11-10ARM: Fix some bugs in the ISA desc and fill out some instructions.Gabe Black
2009-11-10Merge with the head.Gabe Black
2009-11-10Mem: Eliminate the NO_FAULT request flag.Gabe Black
2009-11-10ARM: Implement fault classes.Gabe Black
Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-10ARM: Fix the integer register indexes.Gabe Black
The PC indexes in the various register sets was defined in the section for unaliased registers which was throwing off the indexing. This moves those where they belong. Also, to make detecting accesses to the PC easier and because it's in the same place in all modes, the intRegForceUser function now passes it through as index 15.
2009-11-10X86: Fix bugs in movd implementation.Vince Weaver
Unfortunately my implementation of the movd instruction had two bugs. In one case, when moving a 32-bit value into an xmm register, the lower half of the xmm register was not zero extended. The other case is that xmm was used instead of xmmlm as the source for a register move. My test case didn't notice this at first as it moved xmm0 to eax, which both have the same register number.
2009-11-10X86: Remove double-cast in Cvtf2i micro-opVince Weaver
This double cast led to rounding errors which caused some benchmarks to get the wrong values, most notably lucas which failed spectacularly due to CVTTSD2SI returning an off-by-one value. equake was also broken.
2009-11-08X86: Don't panic on faults on prefetches in SE mode.Gabe Black
2009-11-08X86: Explain what really didn't work with unmapped addresses in SE mode.Gabe Black
2009-11-08X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.Gabe Black
2009-11-08automergeNathan Binkert
2009-11-08ARM: Support forcing load/store multiple to use user registers.Gabe Black
2009-11-08ARM: Simplify the load/store multiple generation code.Gabe Black
Specifically, get rid of the big switch statement so more cases can be handled. Enumerating all the possible settings doesn't scale well. Also do some minor style clean up.
2009-11-08compile: wrap 64bit numbers with ULL() so 32bit compiles workNathan Binkert
In the isa_parser, we need to check case statements.
2009-11-08ARM: Split the condition codes out of the CPSR.Gabe Black
This allows those bits to be renamed while allowing the other fields to control the behavior of the processor.
2009-11-08ARM: Add in more bits for the mon mode.Gabe Black
2009-11-08ARM: Get rid of NumInternalProcRegs.Gabe Black
That constant is a carry over from Alpha and doesn't do anything in ARM.
2009-11-08ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.Gabe Black