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not a cpp file because c99
(which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really
desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment.
src/arch/alpha/isa/fp.isa:
src/arch/sparc/isa/formats/basic.isa:
use m5_fesetround()/m5_fegetround() istead of fenv interface directly
src/arch/sparc/isa/includes.isa:
use base/fenv instead of fenv directly
src/base/SConscript:
add fenv to sconscript
src/base/fenv.hh:
src/base/random.cc:
m5 implementation to standerdize fenv across platforms.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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implementations from using doubles to using concatenated singles.
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test the stub code for instructions.
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parser as a unit.
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unimplemented instructions in their microcode. This is useful if certain variations of an instruction are implemented, but, for instance, it's memory based versions aren't.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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--HG--
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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extra : convert_revision : dba3542ab73cc8ae46347a14ae4c133f1276011c
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IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
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and added some comments to main.isa
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x86-centric stuff.
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seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
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rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa
extra : convert_revision : 5ab40eedf574fce438d9fe90e00a496dc95c8bcf
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sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
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--HG--
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returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.
1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.
In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.
src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
Implemented polymorphic microops and changed around the microcode assembler syntax.
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substitution.
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definitions to make figuring out what's what a little easier:
MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.
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capitalized. Before, it had the first letter capitalized but all the others lower case
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and a real hash function.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : 7be8ebe55a7b11552d78701520f93aa86db1e501
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multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
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into zeep.pool:/z/saidi/work/m5.newmem
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instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support.
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extra : convert_revision : 1a0a4b36afce8255e23e3cdd7a85c1392dda5f72
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Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself.
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actually work.
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--HG--
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
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extra : convert_revision : f3d193dd1e0b82c496d8224f014123b7cb028c02
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
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out-of-order interactions in the 21264.
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useful for x86.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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different sets of inputs.
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what bits decode is done on to reflect where clumps of instructions are.
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--HG--
rename : src/arch/x86/isa/decoder.isa => src/arch/x86/isa/decoder/decoder.isa
extra : convert_revision : a60e7495da6fe99fa2375a3f801f2962c3e41adb
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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--HG--
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