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2018-08-21misc: Appease GCC 8Jason Lowe-Power
GCC 8 adds a number of new warnings to -Wall which generate errors. - Fix memset to 0 for structs by adding casts. - Fix cast with const when the const was ignored. - Fix catch a polymorphic type by value We now compile with GCC 8! Change-Id: Iab70ce11190eee67608fc25c0bedff170152b153 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11949 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2018-08-10arm: Add support for RCpc load-acquire instructions (ARMv8.3)Giacomo Gabrielli
Please note that at the moment these instructions behave like the existing load-acquire instructions, which follow the more conservative RCsc consistency model. This means that the new instructions are _functionally_ correct, but the potential performance improvements enabled by the RCpc model will not be experienced in timing simulations. Change-Id: I04c786ad2941072bf28feba7d2ec6e142c8b74cb Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11989 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-08-02arch-arm: Don't fail to initialise PMU if BP is missingAndreas Sandberg
The branch predictor currently assumes that each CPU has a branch predictor. This isn't true in some cases (e.g., KVM, Atomic). Change-Id: I61e80dca940c2dadba1b812449691c9dba1c06d9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11520 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-07-28arch-riscv: Add xret instructionsAlec Roelke
This patch adds the uret, sret, and mret instructions for use with returning from user-, supervisor-, and machine-level code, respectively. These instructions read the STATUS register to determine the previous privilege level and modify it to re-enable interrupts at the old privilege level. These instructions can only be executed at the corresponding privilege level or higher. Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 Reviewed-on: https://gem5-review.googlesource.com/11136 Maintainer: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de>
2018-07-28arch-riscv: Add support for trap value registerAlec Roelke
RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2018-07-28arch-riscv: Add support for fault handlingAlec Roelke
This patch adds support for handling RISC-V faults, including tracking current and previous execution privilege, correctly switching to the privilege mode specified by CSRs, and setting/storing the PC. It also includes changes introduced by patch #9821, which disables interrupts during handling of a fault. Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 Reviewed-on: https://gem5-review.googlesource.com/9161 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers into the decode tree. They are currently implemented as a generic timer and produces a warning if accessed. Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-16arch-arm: Introduce RAS System RegistersGiacomo Travaglini
Adding RAS Extension System Registers into the decode tree. They are currently unimplemented and produce a warning (not failure) if accessed. Change-Id: I4baeded822c9582a2cb9d5277409b029eb00a962 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11591 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-09arch-riscv: enable rudimentary fs simulationRobert
These changes enable a simple binary to be simulated in full system mode. Additionally, a new fault was implemented. It is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to a reset vector. Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88 Reviewed-on: https://gem5-review.googlesource.com/9061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-09arch-riscv: Fix the srlw and srliw instructions.Austin Harris
Change-Id: I14ccb0655819887db2306fee1188e1c83a991743 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/11669 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2018-06-28arch-arm: Fix incorrect t{0,1}sz field in TTBCRAndreas Sandberg
The t0sz and t1sz fields in TTBCR only are only three bits wide unlike aarch64 which has a 6-bit wide field. The higher bits of the aarch64-equivalent should be treated as RES0. Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11589 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-25syscall_emul: adding symlink system callMatt Sinclair
Change-Id: Iebda05c130b4d2ee8434cad1e703933bfda486c8 Reviewed-on: https://gem5-review.googlesource.com/11490 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-25syscall_emul: adding link system callMatt Sinclair
Change-Id: If8922c2233bbe1f6fce35f64d1a44b91d2cfeed2 Reviewed-on: https://gem5-review.googlesource.com/11489 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-06-22arch-arm: AArch32 execution triggering AArch64 SW BreakGiacomo Travaglini
AArch32 Software Breakpoint (BKPT) can trigger an AArch64 fault when interprocessing if the trapping conditions are met. Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11197 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-22arch-arm: BadMode checking if corresponding EL is implementedGiacomo Travaglini
The old utility function called badMode was only checking if the mode passed as an argument was a recognized mode. It was not checking if the corresponding mode/EL was implemented. That function has been renamed to unknownMode and a new badMode has been introduced. This is used by the cpsrWriteByInstruction function. In this way any try to change the execution mode won't succeed if the mode hasn't been implemented. Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11196 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch: support issuing Atomic Mem Operation (AMO) requestsTuan Ta
This patch adds two new functions named amoMemAtomic used in Atomic CPU model and initiateMemAMO used in Timing CPU models to issue AMO requests to the memory system. Change-Id: I962bdc0e5f25b72c170d96ebc136f29a2b230d5e Reviewed-on: https://gem5-review.googlesource.com/8186 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-14arch-arm: Adapting IllegalExecution fault for AArch32Giacomo Travaglini
The Illegal Execution fault triggered by the setting of processor state PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED exception fault. We are hence copying the UndefinedInstruction AArch32 fields into the IllegalInstSetStateFault. Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10814 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
This patch moves the detection of the Illegal Execution flag (PSTATE.IL) from the tlb translation stage (fetch) to the decoding stage. This is done by adding the illegalExecution field to the PCState. Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch-arm: Read APSR in User ModeGiacomo Travaglini
This patch substitutes reads to the CPSR in user mode (MRS CPSR) to reads to APSR (Application Program Status Register). This is the user level alias for the CPSR. The APSR is a subset of the CPSR. Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10602 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-13arch-arm: Fix missing Request allocationGiacomo Travaglini
This patch is fixing a missing allocation for a Request buffer in the Stage2Translation class. Change-Id: I9ce7b85d3527c5b3cc895eb83e9a39641793b0bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11095 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
Every usage of Request* in the code has been replaced with the RequestPtr alias. This is a preparing patch for when RequestPtr will be the typdefed to a smart pointer to Request rather then a raw pointer to Request. Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10995 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-06arch-arm: Remove dead doingStage2 variable in PT walkerAndreas Sandberg
Change-Id: Iab5ecec56120c725847b2e462fd4793cfac87d3c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10815
2018-06-06arch-arm: Perform stage 2 lookups using the EL2 stateAndreas Sandberg
Change-Id: Ic56b694f22a26e9c208a10e5703d4b5b0900070f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10507 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Respect EL from translation typeAndreas Sandberg
There are cases where instructions request translations in the context of a lower EL. This is currently not respected in the TLB and the page table walker. Fix that. Change-Id: Icd59657a1ecfd8bd75a001bb1a4e41a6f4808a36 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10506 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Fix page size handling when merging stage 1 and 2Andreas Sandberg
The current code to merge translation entries from stage 1 and stage 2 doesn't handle cases where the page sizes at the different stages differ. This change fixes both the case when the hypervisor has a larger page size and when it has a smaller page size. Change-Id: Icdf289005bf1e4de4d91d54643924a38d9d77796 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10505 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06dev, arm: Add support for HYP & secure timersAndreas Sandberg
Change-Id: I1a4849283f9bd5b1856e1378f7cefc33fc14eebd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10023 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Adjust breakpoint EC depending on source stateAndreas Sandberg
The software breakpoint exception class needs to be adjusted depending on the source EL's execution state. This change fixes an incorrect exception class when taking a breakpoint from aarch64. Change-Id: I99d87a04be6bf9ce3a69f6b19969fa006cfd63a4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-29arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOPGiacomo Travaglini
In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: Remove unusued MISCREG_A64_UNIMPLGiacomo Travaglini
In case the decoder fails to find a suitable MiscReg during a MSR/MRS in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra MISCREG_A64_UNIMPL register. Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10503 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: MPIDR.MT = 1 in a multithreaded systemGiacomo Travaglini
MPIDR.MT Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach Change-Id: Ia5e6e65577729c7826227c4574ce690f76454edc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation definedGiacomo Travaglini
In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool of implementation defined registers, provided that reg numbers are in the following range: <op1> is in the range 0 - 7 <CRn> can take the values 11, 15 <CRm> is in the range 0 - 15 <op2> is in the range 0 - 7 Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10501 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: Implement ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for getting the translation table base address when a Host Operating System is running at EL2. (HCR_EL2.E2H = 1) Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10382 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: Add E2H bit to HCR_EL2 System registerGiacomo Travaglini
This patch adds the EL2 Host bit to the HCR_EL2 register. Enables a configuration where a Host Operating System is running in EL2, and the Host Operating System's applications are running in EL0. Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10381 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-24x86: Add op classes to the MediaOps.Gabe Black
The ISA parser had been assuming these microops were all FloatAddOp which is usually not correct. Change-Id: Ic54881d16f16b50c3d6a8c74b94bff9ae3b1f43e Reviewed-on: https://gem5-review.googlesource.com/10541 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Tariq Azmy <tariqslayer01@gmail.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-16arch-arm: Fix semihosting arg count for SYS_GET_CMDLINEAndreas Sandberg
SYS_GET_CMDLINE was declared as having 1 parameter when it is really supposed to have two parameters. Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8 Reported-by: Steve Capper <steve.capper@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10022 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-16arch-arm: Add support for semihosting STDIO redirectionAndreas Sandberg
The Arm Semihosting layer currently assumes that the guest application shares STDIO with gem5. This makes it hard to distinguish application output from gem5's output and makes it impossible to redirect STDIN when running in interactive mode. Add support for custom STDIO redirection when instantiating the Semihosting model. Change-Id: I3411a6b9bfb008ffc3087d8837f59be72bd1e8ae Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10021 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-12arch-riscv: Update CSR implementationsAlec Roelke
This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Performance counters are also not yet implemented, as they do not have specifications. Currently they act as cycle counters. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers based on privilege will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Reviewed-on: https://gem5-review.googlesource.com/7441 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-05-08arch-x86, arch-power: fix calls to bits and insertBitsMatt Sinclair
The bits and insertBits assume the first bit is the larger bit and the last bit is the smaller bit. This commit fixes several X86 and Power calls to these functions that incorrectly assumed that first was the smaller bit. Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01 Reviewed-on: https://gem5-review.googlesource.com/10241 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those registers must be initialized even when the highest Exception Level is using AArch64. Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-03arch-x86: Enable fstatfs for x86_64Tony Gutierrez
Change-Id: Ic871f852c4892f2228f0d9bb3cc5cb66887d9736 Reviewed-on: https://gem5-review.googlesource.com/10201 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-02arch-x86: implement movntps/movntpd SSE instsSteve Reinhardt
These are non-temporal packed SSE stores. Change-Id: I526cd6551b38d6d35010bc6173f23d017106b466 Reviewed-on: https://gem5-review.googlesource.com/9861 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-02x86: Add a ld/st microop flag for marking an access uncacheable.Gabe Black
This percolates down to the memory request object which will have its "UNCACHEABLE" flag set. Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce Reviewed-on: https://gem5-review.googlesource.com/9881 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-02arch-x86: Enable the umask system callTony Gutierrez
Change-Id: I309beb1604657e8d1807ac90458709df57f0f819 Reviewed-on: https://gem5-review.googlesource.com/10161 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception) Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Fix Unknown Instruction disassembleGiacomo Travaglini
Do not print the entire ExtMachInst when disassembling an Unknown Instruction. Change-Id: Icd5908ec0fa430090165b2426372bdeb43c2a155 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10062 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
This patch changes the fault being thrown when MSR/MRS to an unknown Misc register in AArch64. While previously the instruction was decoded as an Unknown instruction (hence not printing any information), it is now decoded as a FailUnimplemented and the unrecognized System register numbers (CRn, op0...) are printed. Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10061 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit CPACR_EL1[31] is RES0 but should be made stateful, since it allows programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1 is removed. Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10046 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
Floating-point trapped exception handlings are not currently supported in gem5, therefore the corresponding bits are RAZ/WI in FCPR. Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10045 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 00:44:34 +0000