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AgeCommit message (Expand)Author
2019-10-02arch-arm: Create helper for sending events (SEV)Giacomo Travaglini
2019-10-02fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.Gabe Black
2019-10-02fastmodel: Implement a custom sendFunctional for CortexA76x1.Gabe Black
2019-10-02x86: Switch from MessageReq and Resp to WriteReq and Resp.Gabe Black
2019-10-02fastmodel: Let the EVS set an attribute for getSendFunctional to return.Gabe Black
2019-10-01fastmodel: Add a gem5Cpu attribute to the CortexA76x1.Gabe Black
2019-10-01fastmodel: Add a utility class which makes it easier to watch signals.Gabe Black
2019-10-01fastmodel: Pull out and simplify the interrupt mechanism in the GIC.Gabe Black
2019-09-27fastmodel: Add glue code which adapts fastmodels to run in gem5.Gabe Black
2019-09-23cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>Jordi Vaquero
2019-09-21x86: Templatize the IntMasterPort.Gabe Black
2019-09-21x86: Templatize IntSlavePort.Gabe Black
2019-09-21x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.Gabe Black
2019-09-20arch-x86: ignore non-temporal hint for movntps/movntpd SSE instsPouya Fotouhi
2019-09-19arch-x86: Change warn to warn_once for NT instructionsHoa Nguyen
2019-09-19arch-arm: PSTATE.PAN changes should inval cached regs in TLBGiacomo Travaglini
2019-09-18arch-arm: Fix Data Abort ISS when caused by Atomic operationGiacomo Travaglini
2019-09-18arch-arm: ISV bit in DataAbort should check for translation stageGiacomo Travaglini
2019-09-18arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1Giacomo Travaglini
2019-09-18arch, x86: Rework the debug faults and microops.Gabe Black
2019-09-13sparc: Fix a warning/error in tlb.cc.Gabe Black
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm: Add explicit AArch64 MiscReg bankingGiacomo Travaglini
2019-09-06arch-arm: Use same template across all MSR instGiacomo Travaglini
2019-09-06arch-arm: SySDC64 Instructions (CMO) using MiscRegIndexGiacomo Travaglini
2019-09-06arch-arm: fix GDB stub after SVECiro Santilli
2019-09-06arch-arm: SGI registers undecoded in AArch32Giacomo Travaglini
2019-09-06arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regsGiacomo Travaglini
2019-09-05arch-x86: Adding warning for movntiPouya Fotouhi
2019-09-05arch-x86: implement movntq/movntdq instructionsPouya Fotouhi
2019-08-30arm,kvm: Fix python imports from global namespaceGiacomo Travaglini
2019-08-28mem: Eliminate the Base(Slave|Master)Port classes.Gabe Black
2019-08-23arch-riscv: fix GDB register cacheAlec Roelke
2019-08-21arch-riscv: Update register fileYifei Liu
2019-08-21arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0Ciro Santilli
2019-08-21arch-arm: Fix implicit fallthrough build errorsChun-Chen TK Hsu
2019-08-20arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currELGiacomo Travaglini
2019-08-20arch-arm: Replace direct use cpsr.el with currEL helperGiacomo Travaglini
2019-08-20arch-arm: Overload currEL helper with CPSR argumentGiacomo Travaglini
2019-08-20arch-arm: Rewrite the currEL helper method to use opModeToELGiacomo Travaglini
2019-08-16x86: Stop CPUID from claiming we support xsave.Gabe Black
2019-08-15x86: Make unsuccessful CPUID instructions zero the result.Gabe Black
2019-08-12arch-arm: Added LD/ST<op> atomic instruction family and SWP instrsJordi Vaquero
2019-08-12arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic funcJordi Vaquero
2019-08-10x86: Move some fixed or dummy config information into X86LocalApic.py.Gabe Black
2019-08-09arch: Bump MaxVecRegLenInBytes to 4096Tony Gutierrez
2019-08-07arch-arm: Add TypeAtomicOp class to be used by new atomic instructionsJordi Vaquero
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