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AgeCommit message (Expand)Author
2020-01-07fastmodel: Implement the vecPredReg accessor functions.Gabe Black
2020-01-07arch,sim: Stop decoding the pseudo inst subfunc value.Gabe Black
2020-01-06arch,sim: Use the guest ABI mechanism with pseudo instructions.Gabe Black
2020-01-06arch-arm: Semihosting, specify files root dirAdrian Herrera
2019-12-30fastmodel: Fix compilation errorsChun-Chen TK Hsu
2019-12-27fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.Gabe Black
2019-12-27fastmodel: Move the ARM IRIS threadcontext into CortexA76.Gabe Black
2019-12-27fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.Gabe Black
2019-12-27fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.Gabe Black
2019-12-27fastmodel: Handle "special" vector regs without calling into IRIS.Gabe Black
2019-12-24fastmodel: Implement readVecRegFlat for ArmThreadContext.Gabe Black
2019-12-24fastmodel: Determine what space to use for breakpoints dynamically.Gabe Black
2019-12-23fastmodel: Implement PC based events.Gabe Black
2019-12-20arch-arm: Fix clang warningsJui-min Lee
2019-12-19arch-arm: Fix decoding of LDFF1x scalar plus scalarAdrià Armejach
2019-12-18arch-arm: Semihosting, fix SYS_FLENAdrian Herrera
2019-12-18arch-arm: Secure EL2 checkingAdrian Herrera
2019-12-18arch-arm: AArch64 trap check, arbitrary ECs/ImmsAdrian Herrera
2019-12-18x86: Fix some bugs with KVM in SE mode on Intel machines.Gabe Black
2019-12-17fastmodel: Tell fast model not to shutdown when time stops.Gabe Black
2019-12-17fastmodel: Implement port proxies.Gabe Black
2019-12-17fastmodel: Create a TLB model which uses IRIS to do translations.Gabe Black
2019-12-17fastmodel: Add an address translation mechanism to the ThreadContext.Gabe Black
2019-12-17fastmodel: Add a header for IRIS MSN constants.Gabe Black
2019-12-11arch-arm: Always initialize SVE memDataGiacomo Travaglini
2019-12-11arch-arm: Avoid creating an empty byteEnable vectorGiacomo Travaglini
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
2019-12-10x86: Stop manually clearing RFLAGS.RF after a system call.Gabe Black
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
2019-12-10arch: Stop using setSyscallArg to set argc and argv.Gabe Black
2019-12-10arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.Gabe Black
2019-12-10arch-arm: Disambuiguate NumFloatV7ArchRegs usageGiacomo Travaglini
2019-12-10arch-arm: Unify VLdmStm behaviour when reg out of indexGiacomo Travaglini
2019-12-10arch-arm: Fix NumVecV7ArchRegs value (64->16)Giacomo Travaglini
2019-12-10arch-arm: Reorder arch/arm/registers.hh constantsGiacomo Travaglini
2019-12-10arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegsGiacomo Travaglini
2019-12-08arch-riscv: set MaxMiscDestRegs to 2Alec Roelke
2019-12-06kvm,arm: Update the KVM ARM v8 CPU to use vector regs.Gabe Black
2019-12-05arch-x86: missing override specifierAndrea Mondelli
2019-12-05arch-x86: Adding LDDQU instructionmarjanfariborz
2019-12-04sparc: Fix the getresuidFunc prototype.Gabe Black
2019-12-04sparc: Fix the predecoder's moreBytes method.Gabe Black
2019-12-03fastmodel: Switch the diagnostic pragmas to GCC from clang.Gabe Black
2019-12-03systemc,fastmodel: Use the gem5_scons error and warning functions.Gabe Black
2019-12-03fastmodel: Suppress a spurious warning on clang for amba_pv.h.Gabe Black
2019-12-01arch-riscv: Fix disassembling of immediate for c.lui instructionIan Jiang
2019-11-28arm: Make sure not to shift off of the end of a uint32_t in KVM.Gabe Black
2019-11-26arch-arm: Make the Tarmac parsed registers case insensitiveGiacomo Travaglini
2019-11-26arch-riscv: Fix immediate decoding for integer shift immediate instructionsIan Jiang
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