summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Collapse)Author
2007-01-27Fixed up printReg so that control registers are printed by name. This is ↵Gabe Black
possible now becauase Ctrl_Base_DepTag gets added into control register numbers. --HG-- extra : convert_revision : d6de3be277127547cd942769cd34a54a4ec8db32
2007-01-26Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 53ee81b099930d4d827db99e2d944ffb8645c706
2007-01-26Make Sparc traceflag even more chattyAli Saidi
some fixes to fp instructions to use the single precision registers if this is an fp op emit fp check code add fpregs to m5legion struct src/arch/sparc/floatregfile.cc: Make Sparc traceflag even more chatty src/arch/sparc/isa/base.isa: add code to check if the fpu is enabled src/arch/sparc/isa/decoder.isa: some fixes to fp instructions to use the single precision registers fix smul again fix subc/subcc/subccc condition code setting src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/mem/util.isa: if this is an fp op emit fp check code src/cpu/exetrace.cc: check fp regs as well as int regs src/cpu/m5legion_interface.h: add fpregs to m5legion struct --HG-- extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
2007-01-26Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.suncc --HG-- extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab
2007-01-26Merge zeep.pool:/z/saidi/work/m5.newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.suncc --HG-- extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
2007-01-26make our code a little more standards compliantAli Saidi
pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-26Fixed the number of integer registers. There are MaxGL+1 sets of globals, ↵Gabe Black
not just MaxGL. --HG-- extra : convert_revision : 6fd090f112611db1e72a1f129dff03687d52930a
2007-01-26Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5 --HG-- extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d
2007-01-26eliminate cpu checkInterrupts bool, it is redundant and unnecessary.Lisa Hsu
--HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
2007-01-25fix smul and sdiv to sign extend, and handle overflow/underflow corretlyAli Saidi
Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back src/arch/sparc/isa/decoder.isa: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/formats/mem/blockmem.isa: Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/includes.isa: Use limits for 32bit underflow/overflow detection src/arch/sparc/tlb.cc: only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync src/arch/sparc/tlb_map.hh: add a print function to dump the tlb lookup table src/cpu/simple/base.cc: if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back --HG-- extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
2007-01-25Fixed a warning that was breaking compilation.Gabe Black
--HG-- extra : convert_revision : 007e83ab452849ce527fe252148e7a1dc423c850
2007-01-24Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 2d7ae62a59b91d735bbac093f8a4ab542ea75eee
2007-01-23use pstate.am to mask off PC/NPC where it needs to +beAli Saidi
check writability of tlb cache entry before using update tagaccess in places I forgot to move the tlb privileged test up since it is higher priority src/arch/sparc/faults.cc: save only 32 bits of PC/NPC if Pstate.am is set src/arch/sparc/isa/decoder.isa: return only 32 bits of PC/NPC if Pstate.am is set increment cleanwin correctly src/arch/sparc/tlb.cc: check writability of cache entry update tagaccess in a few more places move the privileged test up since it is higher priority src/cpu/exetrace.cc: mask off upper bits of pc if pstate.am is set before comparing to legion --HG-- extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
2007-01-22Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmemo3 src/sim/byteswap.hh: Hand Merge --HG-- extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8
2007-01-22clean up fault code a little bitAli Saidi
simplify and make complete some asi checks implement all the twin asis and remove panic checks on their use soft int is supported, so we don't need to print writes to it src/arch/sparc/asi.cc: make AsiIsLittle() be all the little asis. Speed up AsiIsTwin() a bit src/arch/sparc/faults.cc: clean up the do*Fault code.... Make it work like legion, in particular pstate.priv is left alone, not set to 0 like the spec says src/arch/sparc/isa/decoder.isa: implement some more twin ASIs src/arch/sparc/tlb.cc: All the twin asis are implemented, no need to say their not supported anymore src/arch/sparc/ua2005.cc: softint is supported now, no more need to --HG-- extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
2007-01-22Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 21e1bfa49a933f3b39bd2e7bcd873428f9d01a1b
2007-01-22use writeTagAccess() function to unify writing of Tag access registersAli Saidi
Fix extracting of secondary context to shove into tag access register properly sign extend va from 59 bits to 63 (SPARC VA hole) --HG-- extra : convert_revision : 5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
2007-01-21make sure that page bits of VA on tlb insert are 0Ali Saidi
--HG-- extra : convert_revision : f04af884687e9b8631e910cf62cd4a58d035c744
2007-01-20fix InterruptLevel code to return the correct levelAli Saidi
(the bit positition that is set in softint) --HG-- extra : convert_revision : ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
2007-01-20atually set all 64 bits of the retun value to 0Ali Saidi
--HG-- extra : convert_revision : 77bfdf07a49d41a2392f429fdc632c1461ac504c
2007-01-20fix flushw implementationAli Saidi
--HG-- extra : convert_revision : 136b2bddc7cb70cde30e930ad3a13bd56c7162e1
2007-01-20Rearange tlb code to remove some duplicateAli Saidi
Sparc error register should return ull(0) since it's 64 bits Fix PS1 pointer creation to use the ps1 page size rather than ps0 --HG-- extra : convert_revision : fb4ef4b90270c8db676ffe53578acfa3c244526e
2007-01-20Spill and Fill handlers are actually n*4 + the start addressAli Saidi
--HG-- extra : convert_revision : a42f01a84e4b7ba9e6029df50e1612d410a8ba22
2007-01-19Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5 --HG-- extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
2007-01-19some hstick and hintp changes.Lisa Hsu
src/arch/sparc/interrupts.hh: condition hstick matches on HINTP src/arch/sparc/miscregfile.cc: implement HINTP src/arch/sparc/ua2005.cc: don't post interrupt unless it is enabled. --HG-- extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
2007-01-17Allow ASI_LDTX_REALAli Saidi
--HG-- extra : convert_revision : ba1af012ab8ac61a25058977cb7ec511eb2cf3cb
2007-01-17do a linear search for matching tlb entries instead of using map because you ↵Ali Saidi
could be mapping a larger page that intersects many fix for lookup table to keep it consistant with tlb on a replace of a specific entry --HG-- extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32
2007-01-17Implement reading writing of sync fault status register and address registerAli Saidi
--HG-- extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad
2007-01-16In the case of ASI_P or ASI_LDTX_P set primary and skip the other checksAli Saidi
--HG-- extra : convert_revision : e7b21c56eadf4603ab03364741b00c9689492423
2007-01-16Modify ISA and staticInst to support a IsFirstMicroOp flagAli Saidi
Increment instruction count on first micro-op instead of last src/arch/sparc/isa/decoder.isa: Implement a twin load for ASI_LDTX_P(0xe2) src/arch/sparc/isa/formats/mem/blockmem.isa: set the new flag IsFirstMicroOp when needed src/cpu/simple/atomic.cc: Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion) src/cpu/static_inst.hh: Add IsFirstMicroop flag to static insts --HG-- extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
2007-01-11Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5Lisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 src/arch/sparc/ua2005.cc: hand merge between ali and me. --HG-- extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
2007-01-11ua2005.cc:Lisa Hsu
formatting/indentation for case statements src/arch/sparc/ua2005.cc: formatting/indentation for case statements --HG-- extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
2007-01-11ua2005.cc:Lisa Hsu
i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields. src/arch/sparc/ua2005.cc: i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields. --HG-- extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
2007-01-11Add Trap Level Zero to interrupts, remove some unreachable code that I ↵Lisa Hsu
forgot to remove last time. --HG-- extra : convert_revision : 74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
2007-01-10bug fixes to get us to 145m instructionsAli Saidi
src/arch/sparc/intregfile.cc: some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now src/arch/sparc/isa/decoder.isa: fix smul instruction to write Y correctly src/arch/sparc/miscregfile.cc: legion always returns du and dl set, so we need to emulate that for now at least --HG-- extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
2007-01-09quiet/remove some warningsAli Saidi
fix implementation of cwp manipulation implement PS0 and PS1 IMMU asis src/arch/sparc/miscregfile.cc: get rid of some warnings fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are src/arch/sparc/tlb.cc: implement PS0 and PS1 IMMU access ASIs src/arch/sparc/ua2005.cc: make warning less verbose --HG-- extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
2007-01-08pagetable.hh:Lisa Hsu
small fix so ALPHA_FS will build on macs interrupts.hh: small fix for alpha compile src/arch/alpha/interrupts.hh: small fix for alpha compile src/arch/alpha/pagetable.hh: small fix so ALPHA_FS will build on macs --HG-- extra : convert_revision : 5fdbc68caa706d652b51807ac8f6bf58bcf72bdc
2007-01-08the way i understand it, interrupts in m5 is a little bloated. the usage of ↵Lisa Hsu
CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in. src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. --HG-- extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2007-01-08some formatting changes, and update how I do bitfields for HPSTATE and ↵Lisa Hsu
PSTATE to avoid name confusion. src/arch/sparc/faults.cc: 1) s/Resumeable/Resumable/gc 2) s/if(/if (/gc 3) keep variables lowercase 4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv). src/arch/sparc/faults.hh: s/Resumeable/Resumable/ src/arch/sparc/isa_traits.hh: This is unused and unnecessary. src/arch/sparc/miscregfile.hh: add bitfield masks for some important ASRs (HPSTATE, PSTATE). --HG-- extra : convert_revision : f0ffaf48de298758685266dfb90f43aff42e0a2c
2007-01-08fix softint and partially implement hstick interrupts need to figure out how ↵Ali Saidi
to do the acutal interrupting still src/arch/sparc/miscregfile.cc: fix softint and fprs in miscregfile --HG-- extra : convert_revision : cf98bd9c172e20f328f18e07dd05f63f37f14c87
2007-01-05set the softint appropriately on an timer compare interruptAli Saidi
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly src/arch/sparc/faults.cc: there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly src/arch/sparc/faults.hh: correct protection defines src/arch/sparc/ua2005.cc: set the softint appropriately on an timer compare interrupt --HG-- extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
2007-01-04Fix stick compare to work correctly and set checkInterrupts to true at the ↵Ali Saidi
appropriate time turn warnings into dprintfs src/arch/sparc/miscregfile.cc: turn dprintfn into dprintfs --HG-- extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
2007-01-03Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
2006-12-28Implement a stub nnpc for alpha that is read only as npc+4.Gabe Black
--HG-- extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
2006-12-28Fixed NumMiscArchRegs. This is still a magic number, and it should be set ↵Gabe Black
automatically by the miscreg enum. I need to figure out how to do that without including the whole miscregfile.hh and making header spaghetti. --HG-- extra : convert_revision : eb640c9ef10a188b96f6a079f91abc8f67b9d38c
2006-12-27Bug fixes in the TLBAli Saidi
Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48 src/arch/sparc/tlb.cc: Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) src/arch/sparc/tlb.hh: Make our replacement algorithm same as legion (although not same as the spec) src/python/m5/objects/SparcTLB.py: itb should be 64 entries too --HG-- extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-21Stub for SE mode gdb support for MIPS.Gabe Black
--HG-- extra : convert_revision : 2166b511c3615f7a2355f058a624e9ffe8259e65
2006-12-20Fixes to get ALPHA_FS and ALPHA_SE to compile again.Gabe Black
--HG-- extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
2006-12-20Initial work to make remote gdb available in SE mode. This is completely ↵Gabe Black
untested. --HG-- extra : convert_revision : 3ad9a3368961d5e9e71f702da84ffe293fe8adc8
2006-12-20Make sure the "stack_min" variable is page aligned.Gabe Black
--HG-- extra : convert_revision : e78c53778de83bdb2eca13d98d418b17b386ab29
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-14 21:29:56 +0000