Age | Commit message (Collapse) | Author |
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We'll start out with a stbu version of PMSA and switch over to VMSA for the
full implementation.
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These registers provide information about the caches. Since we can't provide
that information, these will be harmlessly inert.
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These enter and leave thumbEE mode. Currently thumbEE mode behaves exactly the
same as Thumb mode, but at least this will make it -look- like we're enter and
leaving it. The actual behavioral changes will be implemented in future
changes.
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This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
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These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory
Barrier).
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This register controls access to the coprocessors. This doesn't actually
implement it, it allows writes which don't turn anything off. In other words,
it allows the simulated program to ask for what it already has.
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