gem5 - gem5

Age	Commit message (Expand)	Author
2019-04-28	mem: Minimize the use of MemObject.	Gabe Black
2019-04-26	arch-arm: updateMiscReg not setting isHyp in aarch64	Giacomo Travaglini
2019-04-26	arm: Factor some repetition out of the ProcessInfo constructor.	Gabe Black
2019-04-25	arm: Fix some style issues in stacktrace.cc.	Gabe Black
2019-04-25	x86: Refactor the ProcessInfo constructor.	Gabe Black
2019-04-25	x86: Fix some style issues in stacktrace.cc.	Gabe Black
2019-04-25	arch-arm: Remove un-needed hyp flag in TLBI operations	Giacomo Travaglini
2019-04-25	arch-arm: Correct target EL field in TLBI operations	Giacomo Travaglini
2019-04-22	sim-se: Enhance clone for X86KvmCPU	Alexandru Dutu
2019-04-22	cpu: Eliminate the ProxyThreadContext class.	Gabe Black
2019-04-11	arch-arm: Enable PMSELR_EL0 read in PMU	Giacomo Travaglini
2019-04-03	misc: Removed inconsistency in O3* debug msgs	Andrea Mondelli
2019-04-02	dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt	Giacomo Travaglini
2019-04-01	dev-arm: Correct cast of template parameter	Andrea Mondelli
2019-03-28	arch-arm: Fix use of bitwise operators on booleans	Javier Setoain
2019-03-28	arch-arm: Fix index generation for VecElem operands	Giacomo Travaglini
2019-03-25	arch-arm: Add missing fall-through defaults	Javier Setoain
2019-03-25	arch-power: Rename program counter registers	Sandipan Das
2019-03-25	arch-power: Simplify doubleword operand types	Sandipan Das
2019-03-22	sim-se: Fixed initialization array size	Tiago Muck
2019-03-21	dev-arm: ambiguous use of getPort()	Andrea Mondelli
2019-03-19	arch, cpu, dev, gpu, mem, sim, python: start using getPort.	Gabe Black
2019-03-14	arch-arm,cpu: Add initial support for Arm SVE	Giacomo Gabrielli
2019-03-11	arch-hsail: changed gen.py shebang from python(3) to python2.7	Ryan Gambord
2019-03-11	arch-arm: Fixing implicit fallthrough build errors	Ryan Gambord
2019-03-01	mem-cache: alias to mem::getMasterPort in TLB class	Andrea Mondelli
2019-03-01	arch-arm: implement floating point aarch32 VCVTA family	Ciro Santilli
2019-02-23	python: Enforce absolute imports for Python 3 compatibility	Andreas Sandberg
2019-02-20	x86: Call the base class's regStats in X86ISA::TLB	Bagus Hanindhito
2019-02-18	arch-generic: Making base TLB class a MemObject	Ivan Pizarro
2019-02-18	arch-arm: Move GICv3 detection at startup time	Giacomo Travaglini
2019-02-13	sim-se: update the arm kernel version	Ayaz Akram
2019-02-12	python: Replace dict.has_key with 'key in dict'	Andreas Sandberg
2019-02-12	python: Don't assume SimObjects live in the global namespace	Andreas Sandberg
2019-02-12	arch-mips: Remove unused Python file	Andreas Sandberg
2019-02-08	riscv: fix AMO, LR and SC instructions	Tuan Ta
2019-02-08	riscv: fixed syscall return value	Tuan Ta
2019-02-08	riscv: ignore nanosleep syscall	Tuan Ta
2019-02-08	arch-riscv: initialize RISC-V's thread pointer register in clone syscall	Tuan Ta
2019-02-08	arch-arm: Fix Virtual interrupts in AArch64	Giacomo Travaglini
2019-02-08	arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30	Giacomo Travaglini
2019-02-08	arch-arm: Allow ArmPPI usage for PMU	Giacomo Travaglini
2019-02-08	arch-arm: Fix initialization of PMU counters	Ruben Ayrapetyan
2019-02-07	arch-riscv: Enable support for riscv 32-bit in SE mode.	Austin Harris
2019-02-06	riscv: remove NonSpeculative flag from fence inst	Tuan Ta
2019-02-06	arch-riscv: Initialize interrupt mask	Tuan Ta
2019-02-05	misc: added missing override specifier	Andrea Mondelli
2019-02-05	riscv: Get rid of ISA specific register types in Interrupts.	Austin Harris
2019-02-01	cpu, arch: Replace the CCReg type with RegVal.	Gabe Black
2019-01-31	power: Get rid of some ISA specific register types.	Gabe Black