Age | Commit message (Collapse) | Author |
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ISA independent by making it use the #define for branch delay slots (and NNPC)
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base kernel_stats to base_kernel_stats
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SConstruct:
Put the code to make a switching header directory into a function so they are easy to make.
src/arch/SConscript:
Replace switching header code with the new function call.
src/kern/SConscript:
Created a new switching header directory in kern, and moved the declaration of some source files here.
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rename : src/kern/kernel_stats.cc => src/kern/base_kernel_stats.cc
rename : src/kern/kernel_stats.hh => src/kern/base_kernel_stats.hh
extra : convert_revision : 98f5320a5ade567c3e4f67fef123dfb0c5122545
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/SConscript:
SCCS merged
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but isn't tested. Other architectures will not.
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extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
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from TheISA:: rather than AlphaISA::
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extra : convert_revision : 17c143d3cbc2f58a7a9d01366a8f649810ff7f33
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Alpha and SPARC and put SConscripts in them.
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rename : src/base/kgdb.h => src/arch/alpha/kgdb.h
rename : src/dev/alpha_access.h => src/dev/alpha/access.h
rename : src/dev/alpha_console.cc => src/dev/alpha/console.cc
rename : src/dev/alpha_console.hh => src/dev/alpha/console.hh
extra : convert_revision : a7dd466308cb83edc40528689aacb72413089cdf
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into zeep.pool:/z/saidi/work/m5.newmem
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SConstruct:
Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
solaris doesn't have random(), so use rint with the correct rounding mode
if we're compiling on solaris
src/base/stats/flags.hh:
u_int32_t??
src/base/time.hh:
grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
we don't need to include stdint here
src/sim/byteswap.hh:
the method to detect endianness on Solaris is a little more complex...
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because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this.
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PowerOnReset fault to kick start the CPU.
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could be improved and syscalls could be called from the trap's invoke method.
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extra : convert_revision : a1cdd35c74f6e85f42a04061b466ec7617da8ac2
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src/arch/sparc/faults.cc:
Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.
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system.cc
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are in PAL mode, however.
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records when interrupts are requested, and returns an interrupt to execute if the
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
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src/arch/alpha/utility.hh:
For now makeExtMI will be specific to the ISA.
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extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
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extra : convert_revision : 84e25abd4bb2de0c877c883804d39feb019c7030
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file functions to not take faults
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corresponding to an IPR is readable or writable.
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code all over the place.
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the miscreg index of a specific IPR.
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functions.
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more neutral names.
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in the future for micro insts.
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src/arch/sparc/isa/decoder.isa:
Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
Reorganized things a bit to better support cas
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extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
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the integer microcode register.
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