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AgeCommit message (Expand)Author
2019-10-15arch-x86: Make LFENCE a serializing instructionIsaac Richter
2019-10-15x86: De-x86ify the IntMasterPort.Gabe Black
2019-10-14x86: Simplify and consolidate the code that assembles an MSI on x86.Gabe Black
2019-10-14fastmodel: Expose all CPU communication ports from the GIC.Gabe Black
2019-10-12x86: Stop using and delete the x86 IntDevice class.Gabe Black
2019-10-12arch,base: Separate the idea of a memory image and object file.Gabe Black
2019-10-10arch,base: Stop loading the interpreter in ElfObject.Gabe Black
2019-10-10arch-arm: Move generateDtb to ArmSystemGiacomo Travaglini
2019-10-10dev-arm, configs: Remove RealViewPBX platformGiacomo Travaglini
2019-10-10arch, base: Stop assuming object files have three segments.Gabe Black
2019-10-09fastmodel: Export GICV3Comms directly.Gabe Black
2019-10-09arch-mips,arch-riscv,base: Get rid of the unused HexFile class.Gabe Black
2019-10-09base: Rename Section to Segment, and some of its members.Gabe Black
2019-10-08base: Get rid of the unused global pointer in object files.Gabe Black
2019-10-07fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.Gabe Black
2019-10-07kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCRCiro Santilli
2019-10-03arch-arm: Annotate CM flag in AA64 CM InstructionsGiacomo Travaglini
2019-10-03arch-arm: Set CM bit in DataAbortGiacomo Travaglini
2019-10-02arch-arm: Create helper for sending events (SEV)Giacomo Travaglini
2019-10-02fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.Gabe Black
2019-10-02fastmodel: Implement a custom sendFunctional for CortexA76x1.Gabe Black
2019-10-02x86: Switch from MessageReq and Resp to WriteReq and Resp.Gabe Black
2019-10-02fastmodel: Let the EVS set an attribute for getSendFunctional to return.Gabe Black
2019-10-01fastmodel: Add a gem5Cpu attribute to the CortexA76x1.Gabe Black
2019-10-01fastmodel: Add a utility class which makes it easier to watch signals.Gabe Black
2019-10-01fastmodel: Pull out and simplify the interrupt mechanism in the GIC.Gabe Black
2019-09-27fastmodel: Add glue code which adapts fastmodels to run in gem5.Gabe Black
2019-09-23cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>Jordi Vaquero
2019-09-21x86: Templatize the IntMasterPort.Gabe Black
2019-09-21x86: Templatize IntSlavePort.Gabe Black
2019-09-21x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.Gabe Black
2019-09-20arch-x86: ignore non-temporal hint for movntps/movntpd SSE instsPouya Fotouhi
2019-09-19arch-x86: Change warn to warn_once for NT instructionsHoa Nguyen
2019-09-19arch-arm: PSTATE.PAN changes should inval cached regs in TLBGiacomo Travaglini
2019-09-18arch-arm: Fix Data Abort ISS when caused by Atomic operationGiacomo Travaglini
2019-09-18arch-arm: ISV bit in DataAbort should check for translation stageGiacomo Travaglini
2019-09-18arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1Giacomo Travaglini
2019-09-18arch, x86: Rework the debug faults and microops.Gabe Black
2019-09-13sparc: Fix a warning/error in tlb.cc.Gabe Black
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm: Add explicit AArch64 MiscReg bankingGiacomo Travaglini
2019-09-06arch-arm: Use same template across all MSR instGiacomo Travaglini
2019-09-06arch-arm: SySDC64 Instructions (CMO) using MiscRegIndexGiacomo Travaglini
2019-09-06arch-arm: fix GDB stub after SVECiro Santilli
2019-09-06arch-arm: SGI registers undecoded in AArch32Giacomo Travaglini
2019-09-06arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regsGiacomo Travaglini
2019-09-05arch-x86: Adding warning for movntiPouya Fotouhi
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