gem5 - gem5

Age	Commit message (Collapse)	Author
2011-03-29	Power: Fix compilation.	Gabe Black

2011-03-26	mips: cleanup ISA-specific code	Korey Sewell
	*** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway.
2011-03-25	Arm: Add in a missing miscRegName.	Gabe Black

2011-03-24	Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.	Gabe Black

2011-03-24	Arm: Get rid of the unused copyStringArray32 method from Arm process classes.	Gabe Black

2011-03-24	ISA parser: Set up op_src_decl and op_dest_decl for pc operands.	Gabe Black

2011-03-17	ARM: Add minimal ARM_SE support for m5threads.	Chris Emmons
	Updated some of the assembly code sequences to use armv7 instructions and coprocessor 15 for storing the TLS pointer.
2011-03-17	ARM: Fix subtle bug in LDM.	Ali Saidi
	If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17	ARM: Implement the Instruction Set Attribute Registers (ISAR).	Ali Saidi
	The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values
2011-03-17	ARM: Identify branches as conditional or unconditional and direct or indirect.	Ali Saidi

2011-03-17	ARM: Fix small bug with VLDM/VSTM instructions.	Ali Saidi

2011-03-17	ARM: Detect and skip udelay() functions in linux kernel.	Ali Saidi
	This change speeds up booting, especially in MP cases, by not executing udelay() on the core but instead skipping ahead tha amount of time that is being delayed.
2011-03-17	ARM: Allow conditional quiesce instructions.	Ali Saidi
	This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
2011-03-17	ARM: Fix RFE macrop.	Matt Horsnell
	This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.
2011-03-17	ARM: Rename registers used as temporary state by microops.	Matt Horsnell

2011-03-17	O3: Send instruction back to fetch on squash to seed predecoder correctly.	Ali Saidi

2011-03-17	ARM: Previous change didn't end up setting instFlags, this does.	Ali Saidi

2011-03-08	Alpha: Fix the datatypes of some values read from the simulated kernel.	Yi Xiang

2011-03-02	X86: Use the npc as the pc when doing a nativetrace, not what M5 considers ↵	Gabe Black
	the pc.
2011-03-02	X86: Decode the mysterious and elusive ffreep x87 instruction.	Gabe Black
	The internet says this instruction was created by accident when an Intel CPU failed to decode x87 instructions properly. It's been documented on a few rare occasions and has generally worked to ensure backwards compatability. One source claims that the gcc toolchain is basically the only thing that emits it, and that emulators/binary translators like qemu and bochs implement it. We won't actually implement it here since we're hardly implementing any other x87 instructions either. If we were to implement it, it would behave the same as ffree but then also pop the register stack. http://www.pagetable.com/?p=16
2011-03-01	Spelling: Fix the a spelling error by changing mmaped to mmapped.	Gabe Black
	There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. --HG-- rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
2011-03-01	X86: Mark IO reads and writes as non-speculative.	Gabe Black

2011-03-01	X86: Mark prefetches as such in their instruction and request flags.	Gabe Black

2011-02-27	X86: If PCI config space is disabled, pass through to regular IO addresses.	Gabe Black

2011-02-27	X86: Use regular read requests in the walker instead of read exclusive.	Gabe Black

2011-02-23	ARM: Set ITSTATE correctly after FlushPipe	Ali Saidi

2011-02-23	ARM: This panic can be hit during misspeculation so it can't exist.	Ali Saidi

2011-02-23	ARM: Bad interworking warn way to noisy when running real code w/misspeculation.	Ali Saidi

2011-02-23	ARM: NEON instruction templates modified to set the predicate flag to false ↵	Giacomo Gabrielli
	when needed.
2011-02-23	ARM: Squash state on FPSCR stride or len write.	Ali Saidi

2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell

2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi

2011-02-23	ARM: Fix bug that let two table walks occur in parallel.	Ali Saidi

2011-02-23	ARM: Make Noop actually decode to a noop and set it's instflags.	Ali Saidi

2011-02-23	ARM: Delete OABI syscall handling.	Ali Saidi
	We only support EABI binaries, so there is no reason to support OABI syscalls. The loader detects OABI calls and fatal() so there is no reason to even check here.
2011-02-23	ARM: Reset simulation statistics when pref counters are reset.	Ali Saidi
	The ARM performance counters are not currently supported by the model. This patch interprets a 'reset performance counters' command to mean 'reset the simulator statistics' instead.
2011-02-23	ARM: Adds dummy support for a L2 latency miscreg.	Ali Saidi

2011-02-15	X86: Get rid of "inline" on the MicroPanic constructor in decoder.cc.	Gabe Black
	This was making certain versions of gcc omit the function from the object file which would break the build.
2011-02-13	X86: Detect branches taking into account instruction size.	Gabe Black
	The size of the current instruction determines what the npc should be if there's no branching.
2011-02-13	X86: Put the result used for flags in an intermediate variable.	Gabe Black
	Using the destination register directly causes the ISA parser to treat it as a source even if none of the original bits are used.
2011-02-13	X86: Don't read in dest regs if all bits are replaced.	Gabe Black
	In x86, 32 and 64 bit writes to registers in which registers appear to be 32 or 64 bits wide overwrite all bits of the destination register. This change removes false dependencies in these cases where the previous value of a register doesn't need to be read to write a new value. New versions of most microops are created that have a "Big" suffix which simply overwrite their destination, and the right version to use is selected during microop allocation based on the selected data size. This does not change the performance of the O3 CPU model significantly, I assume because there are other false dependencies from the condition code bits in the flags register.
2011-02-13	X86: On a bad microopc, return a microop that returns a fault that panics.	Gabe Black
	This way a bad micropc will have to get all the way to commit before killing the simulation. This accounts for misspeculated branches.
2011-02-13	X86: Define fault objects to carry debug messages.	Gabe Black
	These faults can panic/warn/warn_once, etc., instead of instructions doing that themselves directly. That way, instructions can be speculatively executed, and only if they're actually going to commit will their fault be invoked and the panic, etc., happen.
2011-02-13	X86: Only reset npc to reflect instruction length once.	Gabe Black
	When redirecting fetch to handle branches, the npc of the current pc state needs to be left alone. This change makes the pc state record whether or not the npc already reflects a real value by making it keep track of the current instruction size, or if no size has been set.
2011-02-12	inorder: remove unused isa ops	Korey Sewell
	pass/fail ops were used for testing but arent part of isa
2011-02-11	O3: Fix a few bugs in the TableWalker object.	Giacomo Gabrielli
	Uncacheable requests were set as such only in atomic mode. currState->delayed is checked in place of currState->timing for resetting currState in atomic mode.
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
	Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
2011-02-07	X86: Obey the wp bit of CR0.	Tim Harris
	If cr0.wp ("write protect" bit) is clear then do not generate page faults when writing to write-protected pages in kernel mode.
2011-02-07	X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.	Tim Harris
	During SYSCALL_64, use dataSize=8 when handling new rip (ref http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit address)
2011-02-07	X86: Fix JMP_FAR_I to unpack a far pointer correctly.	Tim Harris
	JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like it should, and also putting the components in the wrong registers for use by other microcode.