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2011-02-15X86: Get rid of "inline" on the MicroPanic constructor in decoder.cc.Gabe Black
This was making certain versions of gcc omit the function from the object file which would break the build.
2011-02-13X86: Detect branches taking into account instruction size.Gabe Black
The size of the current instruction determines what the npc should be if there's no branching.
2011-02-13X86: Put the result used for flags in an intermediate variable.Gabe Black
Using the destination register directly causes the ISA parser to treat it as a source even if none of the original bits are used.
2011-02-13X86: Don't read in dest regs if all bits are replaced.Gabe Black
In x86, 32 and 64 bit writes to registers in which registers appear to be 32 or 64 bits wide overwrite all bits of the destination register. This change removes false dependencies in these cases where the previous value of a register doesn't need to be read to write a new value. New versions of most microops are created that have a "Big" suffix which simply overwrite their destination, and the right version to use is selected during microop allocation based on the selected data size. This does not change the performance of the O3 CPU model significantly, I assume because there are other false dependencies from the condition code bits in the flags register.
2011-02-13X86: On a bad microopc, return a microop that returns a fault that panics.Gabe Black
This way a bad micropc will have to get all the way to commit before killing the simulation. This accounts for misspeculated branches.
2011-02-13X86: Define fault objects to carry debug messages.Gabe Black
These faults can panic/warn/warn_once, etc., instead of instructions doing that themselves directly. That way, instructions can be speculatively executed, and only if they're actually going to commit will their fault be invoked and the panic, etc., happen.
2011-02-13X86: Only reset npc to reflect instruction length once.Gabe Black
When redirecting fetch to handle branches, the npc of the current pc state needs to be left alone. This change makes the pc state record whether or not the npc already reflects a real value by making it keep track of the current instruction size, or if no size has been set.
2011-02-12inorder: remove unused isa opsKorey Sewell
pass/fail ops were used for testing but arent part of isa
2011-02-11O3: Fix a few bugs in the TableWalker object.Giacomo Gabrielli
Uncacheable requests were set as such only in atomic mode. currState->delayed is checked in place of currState->timing for resetting currState in atomic mode.
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
2011-02-07X86: Obey the wp bit of CR0.Tim Harris
If cr0.wp ("write protect" bit) is clear then do not generate page faults when writing to write-protected pages in kernel mode.
2011-02-07X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.Tim Harris
During SYSCALL_64, use dataSize=8 when handling new rip (ref http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit address)
2011-02-07X86: Fix JMP_FAR_I to unpack a far pointer correctly.Tim Harris
JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like it should, and also putting the components in the wrong registers for use by other microcode.
2011-02-07X86: Read the LDT/GDT at CPL0 when executing an iret.Tim Harris
During iret access LDT/GDT at CPL0 rather than after transition to user mode (if I'm reading the Intel IA-64 architecture spec correctly, the contents of the descriptor table are read before the CPL is updated).
2011-02-07X86: Fix compiling vtophys.ccGabe Black
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06dev: fixed bugs to extend interrupt capability beyond 15 coresBrad Beckmann
2011-02-06x86: Timing support for pagetable walkerJoel Hestness
Move page table walker state to its own object type, and make the walker instantiate state for each outstanding walk. By storing the states in a queue, the walker is able to handle multiple outstanding timing requests. Note that functional walks use separate state elements.
2011-02-06x86: Add checkpointing capability to arch componentsJoel Hestness
Add checkpointing capability to the x86 interrupt device and the TLBs
2011-02-06x86: implements vtophysJoel Hestness
Calls walker to look up virt. to phys. page mapping
2011-02-06IntDev: packet latency fixJoel Hestness
The x86 local apic now includes a separate latency parameter for interrupts.
2011-02-06MessagePort: implement the virtual recvTiming function to avoid double pkt ↵Joel Hestness
delete Double packet delete problem is due to an interrupt device deleting a packet that the SimpleTimingPort also deletes. Since MessagePort descends from SimpleTimingPort, simply reimplement the failing code from SimpleTimingPort: recvTiming.
2011-02-06x86: set IsCondControl flag for the appropriate microopsBrad Beckmann
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
--HG-- rename : src/sim/fault.hh => src/sim/fault_fwd.hh
2011-02-02X86: Get rid of the stupd microop.Gabe Black
2011-02-02X86: Replace the stupd microop with a store/update sequence.Gabe Black
2011-01-18O3: Fix itstate prediction and recovery.Matt Horsnell
Any change of control flow now resets the itstate to 0 mask and 0 condition, except where the control flow alteration write into the cpsr register. These case, for example return from an iterrupt, require the predecoder to recover the itstate. As there is a window of opportunity between the return from an interrupt changing the control flow at the head of the pipe and the commit of the update to the CPSR, the predecoder needs to be able to grab the ITstate early. This is now handled by setting the forcedItState inside a PCstate for the control flow altering instruction. That instruction will have the correct mask/cond, but will not have a valid itstate until advancePC is called (note this happens to advance the execution). When the new PCstate is copy constructed it gets the itstate cond/mask, and upon advancing the PC the itstate becomes valid. Subsequent advancing invalidates the state and zeroes the cond/mask. This is handled in isolation for the ARM ISA and should have no impact on other ISAs. Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details.
2011-01-18O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.Matt Horsnell
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path.
2011-01-18O3: Fixes the way prefetches are handled inside the iew unit.Matt Horsnell
This patch prevents the prefetch being added to the instCommit queue twice.
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-18O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.Min Kyu Jeong
When this condition occurs the cpu should restart the fetch stage to fetch from the original execution path. Fault handling in the commit stage is cleaned up a little bit so the control flow is simplier. Finally, if an instruction is being used to carry a fault it isn't executed, so the fault propagates appropriately.
2011-01-18ARM: Use an actual NOP instead of a instruction that happens to do nothingAli Saidi
2011-01-18ARM: fix mismatched new/delete.Ali Saidi
2011-01-15SPARC: Adjust the "call" instruction so R15 doesn't get marked as a source.Gabe Black
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2011-01-07scons: show sources and targets when building, and colorize output.Steve Reinhardt
I like the brevity of Ali's recent change, but the ambiguity of sometimes showing the source and sometimes the target is a little confusing. This patch makes scons typically list all sources and all targets for each action, with the common path prefix factored out for brevity. It's a little more verbose now but also more informative. Somehow Ali talked me into adding colors too, which is a whole 'nother story.
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-09ARM: Get rid of some unused FP operands.Gabe Black
2010-12-08Alpha: Take advantage of new PCState syntax.Gabe Black
2010-12-08MIPS: Take advantage of new PCState syntax.Gabe Black
2010-12-08POWER: Take advantage of new PCState syntax.Gabe Black
2010-12-08SPARC: Take advantage of new PCState syntax.Gabe Black
2010-12-08X86: Take advantage of new PCState syntax.Gabe Black
2010-12-07ISA: Get the parser to support pc state components more elegantly.Gabe Black
2010-12-07O3: Support squashing all state after special instructionAli Saidi
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply marking the instruction as Serializing isn't enough beacuse that only stops rename. This provides a mechanism to squash all the instructions and refetch them
2010-12-07O3: Make all instructions that write a misc. register not perform the write ↵Giacomo Gabrielli
until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong