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AgeCommit message (Expand)Author
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-08util: add m5_fail op.Lluís Vilanova
2013-01-08arm: add access syscall for ARM SE modeMitch Hayenga
2013-01-07cpu: Flush TLBs on switchOut()Andreas Sandberg
2013-01-07arm: Invalidate cached TLB configuration in drainResumeAndreas Sandberg
2013-01-07arm: Fix draining of the pagetable walker when squashingAndreas Sandberg
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
2013-01-07arch: Add support for invalidating TLBs when drainingAndreas Sandberg
2013-01-07arch: Fix broken M5VarArgsFault initializationAndreas Sandberg
2013-01-07base: Encapsulate the underlying fields in AddrRangeAndreas Hansson
2013-01-07arm: Make ID registers ISA parametersAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2013-01-04X86: Move address based decode caching in front of the predecoder.Gabe Black
2013-01-04SPARC: Keep a copy of the current ASI in the decoder.Gabe Black
2013-01-04ARM: Keep a copy of the fpscr len and stride fields in the decoder.Gabe Black
2012-12-30x86: implement x87 fp instruction fnstswNilay Vaish
2012-12-30x86: implement x87 fp instruction fsincosNilay Vaish
2012-12-12arm: set uopSet_uop as conditional or unconditional controlNathanael Premillieu
2012-12-12arm: set movret_uop as conditional or unconditional controlNathanael Premillieu
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02mips: Remove unused Python fileAndreas Sandberg
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-11-02ISA: generic Linux thread info supportDam Sunwoo
2012-10-25arm: Use table walker clock that is inherited from CPUAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Checkpoint: Make system serialize call childrenAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-09-25ARM: added support for flattened device tree blobsDam Sunwoo
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-25arm: Use a static_assert to test that miscRegName[] is completeAndreas Sandberg
2012-09-25ARM: Inst writing to cntrlReg registers not set as control instNathanael Premillieu
2012-09-25ARM: Predict target of more instructions that modify PC.Ali Saidi
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-11X86: make use of register predicationNilay Vaish
2012-09-11x86: Add a separate register for D flag bitNilay Vaish
2012-06-03ISA Parser: Allow predication of source and destination registersNilay Vaish
2012-09-10NetBSD: Build on NetBSDPalle Lyckegaard
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-21Device: Remove overloaded pio_latency parameterAndreas Hansson
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-08-16Alpha System: override startup(), instead of loadState()Nilay Vaish
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-08-15sysemul: bump all linux versions of for syscal emulation to 3.0.Ali Saidi
2012-08-06syscall emulation: Enabled getrlimit and getrusage for x86.Marc Orr
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