| Age | Commit message (Expand) | Author |
|---|
| 2017-12-19 | arch-arm: Change casting type from reinterpret to static | Giacomo Travaglini |
| 2017-12-14 | arch-riscv: Define AT_RANDOM properly | Alec Roelke |
| 2017-12-14 | arch-riscv: Increase maximum stack size | Alec Roelke |
| 2017-12-14 | misc: Updates for gcc7.2 for x86 | Jason Lowe-Power |
| 2017-12-14 | x86: Use operand size 4 when it would be 2 for cmpxchg8b. | Gabe Black |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-13 | x86: Rework how "split" loads/stores are handled. | Gabe Black |
| 2017-12-08 | arm: Change access permission in TPIDRURO and TPIDRURW | Giacomo Travaglini |
| 2017-12-08 | x86,misc: add additional info on faulting X86 instruction, fetched PC | Matt Sinclair |
| 2017-12-07 | arch-riscv: Move compressed ops out of ISA | Alec Roelke |
| 2017-12-06 | x86: Split apart x87's FSW and TOP, and add a missing break. | Gabe Black |
| 2017-12-05 | x86: LOOP's operand size defaults to 64 bits in 64 bit mode. | Gabe Black |
| 2017-12-05 | arm: Add support for the dc {civac, cvac, cvau, ivac} instr | Nikos Nikoleris |
| 2017-12-05 | arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions | Nikos Nikoleris |
| 2017-12-05 | arm: Add CMO support for Non-Cacheable memory | Nikos Nikoleris |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-12-01 | arm: Enable ns registers access in secure mode | Giacomo Travaglini |
| 2017-11-30 | arch-riscv: use sext rather than manual masks | Alec Roelke |
| 2017-11-30 | arch-riscv: Remove spaces around ea_code | Alec Roelke |
| 2017-11-29 | arch-riscv: Add missing license paragraphs | Alec Roelke |
| 2017-11-29 | arch-riscv: Remove static parts of AMOs out of ISA | Alec Roelke |
| 2017-11-29 | arch-riscv: Move parts of mem insts out of ISA | Alec Roelke |
| 2017-11-29 | arch-riscv: Move unknown out of ISA description | Alec Roelke |
| 2017-11-29 | arch-riscv: Move standard ops out of ISA | Alec Roelke |
| 2017-11-28 | arch-arm: Add haveEL pseudocode function | Giacomo Travaglini |
| 2017-11-28 | arch-arm: Add assertions when extracting an ArmSystem from a TC | Giacomo Travaglini |
| 2017-11-28 | arch-riscv: Move static_inst into a directory | Alec Roelke |
| 2017-11-22 | arch-arm: Add support for the brk instruction | Andreas Sandberg |
| 2017-11-22 | arch-arm: HVC instruction undefined in secure EL1 | Giacomo Travaglini |
| 2017-11-22 | arch-riscv: Add missing system calls | Alec Roelke |
| 2017-11-22 | sparc: Move integer StaticInst base classes out of the ISA desc. | Gabe Black |
| 2017-11-22 | sparc: Move the mem base classes out of the ISA description. | Gabe Black |
| 2017-11-22 | sparc: Move the microop/macroop base classes out of the ISA desc. | Gabe Black |
| 2017-11-22 | sparc: Return debug faults from unimplemented instructions. | Gabe Black |
| 2017-11-22 | sparc: Pull the unimplemented formats out of the ISA description. | Gabe Black |
| 2017-11-22 | sparc: Pull the "Uknown" StaticInst class out of the ISA description. | Gabe Black |
| 2017-11-22 | sparc: Pull most of the Nop format out of the ISA description. | Gabe Black |
| 2017-11-22 | sparc: Pull more StaticInst base classes out of the ISA desc. | Gabe Black |
| 2017-11-22 | sparc: Pull flat static instruction classes out of the ISA. | Gabe Black |
| 2017-11-21 | arch-arm: ArmPMU refactor | Jose Marinho |
| 2017-11-21 | arch-arm: Do not increment PMU cycle event in WFI/WFE | Jose Marinho |
| 2017-11-21 | arch-arm: Fix MCR/MRC disassemble | Giacomo Travaglini |
| 2017-11-21 | arch-arm: Fix MSR/MRS disassemble | Giacomo Travaglini |
| 2017-11-20 | arch-arm: Ensure counters keep events on checkpoint resume | Jose Marinho |
| 2017-11-20 | sparc: Pull StaticInst base classes out of the ISA description. | Gabe Black |
| 2017-11-17 | sim: Implement load_addr_mask auto-calculation | Geoffrey Blake |
| 2017-11-16 | arch, arm: Print value being ignored on DummyISA write | Sean McGoogan |
| 2017-11-15 | arch-arm: Dsb instruction shouldn't flush the pipeline | Giacomo Travaglini |
| 2017-11-15 | arch-arm: Writes to DCCMVAC shouldn't flush pipeline | Giacomo Travaglini |
